BSPDN

PCB Design | PDN Optimization: Balancing Performance and Cost in SoC Design

by
PCB Design | PDN Optimization: Balancing Performance and Cost in SoC Design

With the continuous evolution of System-on-Chip (SoC) devices, modern electronic systems have gained unprecedented computing power while also presenting increasingly complex power distribution challenges. Especially in the context of companies striving to accelerate time-to-market and control costs, optimizing the Power Delivery Network (PDN) has become a key factor in successful product development. Author Zach Caprai … Read more

The Competition Between Gate-All-Around (GAA) and Buried Power Distribution Network (BSPDN) Technologies at the 2nm Node

by
The Competition Between Gate-All-Around (GAA) and Buried Power Distribution Network (BSPDN) Technologies at the 2nm Node

Fundamentals of Buried Power Distribution Network (BSPDN) In addition to Gate-All-Around (GAA) transistors, BSPDN is another key innovation in next-generation logic process technology. In all current digital logic process technologies, transistors are first fabricated on the wafer, followed by the creation of dozens of metal layers that power the transistors and transmit signals between them … Read more

The Great Revolution in Chip Power Supply: What Are the Benefits of Backside Power Delivery Network (BSPDN)?

by
The Great Revolution in Chip Power Supply: What Are the Benefits of Backside Power Delivery Network (BSPDN)?

In the world of chip manufacturing, the race at the nanoscale has never ceased. As we transition from 7nm to 5nm, 3nm, and even more advanced processes, an unexpected challenge has emerged: the power delivery network is starting to occupy the front space of the chip. It’s like a bustling city where utility poles and … Read more

Analysis of the Impact of Back Power Distribution Network (BSPDN) on Power/Performance/Area/Temperature (PPAT)

by
Analysis of the Impact of Back Power Distribution Network (BSPDN) on Power/Performance/Area/Temperature (PPAT)

Literature from IMEC, published in 2022, focuses on the impact of BSPDN on PPAT.The front end (FEOL) is an active driver of chip power/performance/area (PPA). As scaling approaches the physical limits of semiconductor devices, the back end (BEOL)/middle end (MEOL)/packaging becomes increasingly important for PPA improvements in chips/systems. At 2nm and below, BSPDN back interconnects … Read more

Analysis of the Impact of Back Power Distribution Network (BSPDN) on Power/Performance/Area/Temperature (PPAT)

by
Analysis of the Impact of Back Power Distribution Network (BSPDN) on Power/Performance/Area/Temperature (PPAT)

This literature is from IMEC, published in 2022, focusing on the impact of BSPDN on the study of PPAT.The front end (FEOL) is an active driver of chip power/performance/area (PPA). As scaling approaches the physical limits of semiconductor devices, the back end (BEOL)/middle end (MEOL)/packaging becomes increasingly important for PPA improvements in chips/systems. At 2nm … Read more

Backside Power Delivery Technology (BSPDN)

by
Backside Power Delivery Technology (BSPDN)

Backside Power Delivery Technology (BSPDN) Backside Power Delivery Technology requires separation of signals and power, placing the signal structure and power structure from wafer fabrication on the front and back of the wafer. Illustration of Mainstream Chip Structure and Backside Power Chip Structure Mainstream Chip Structure Traditionally, the power and signal structures in chips are … Read more