semiconductor technology

Democratizing 3D Integration: A Low-Cost Prototyping Solution Based on Chip-Level Thinning, Through-Silicon Vias (TSV), and Meta Bonding

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Democratizing 3D Integration: A Low-Cost Prototyping Solution Based on Chip-Level Thinning, Through-Silicon Vias (TSV), and Meta Bonding

Original link: https://xplorestaging.ieee.org/document/11007580【Abstract】 Three-dimensional integrated circuit (3D-IC) technology, with its vertical interconnections through silicon vias (TSV), has become central to advanced semiconductor devices. However, the initial development costs are prohibitively high, primarily due to the substantial investment required for wafer-level TSV processes. This study proposes…

New Forces in the Rankings: Pure Semiconductor – Building a Domestic Silicon Carbide Symbiotic Network

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New Forces in the Rankings: Pure Semiconductor - Building a Domestic Silicon Carbide Symbiotic Network

This is a testament to the glory of the city, a historical epic that stirs the industrial landscape. Since its emergence in 2005, the “Ningbo Entrepreneurship and Innovation Ranking” has measured the industrial leap along the East China Sea over twenty years, inscribing the legend of entrepreneurship and innovation in Ningbo, continuously projecting the strong … Read more

Analysis of the Impact of Back Power Distribution Network (BSPDN) on Power/Performance/Area/Temperature (PPAT)

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Analysis of the Impact of Back Power Distribution Network (BSPDN) on Power/Performance/Area/Temperature (PPAT)

This literature is from IMEC, published in 2022, focusing on the impact of BSPDN on the study of PPAT.The front end (FEOL) is an active driver of chip power/performance/area (PPA). As scaling approaches the physical limits of semiconductor devices, the back end (BEOL)/middle end (MEOL)/packaging becomes increasingly important for PPA improvements in chips/systems. At 2nm … Read more

Current Status of the Supply Chain for AI Chip Ecosystem

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Current Status of the Supply Chain for AI Chip Ecosystem

China is accelerating the establishment of its artificial intelligence chip ecosystem as U.S. restrictions take effect. Here is the current status of its supply chain: Key Points U.S.-led export controls have excluded China from key segments of the AI chip supply chain. Many chip experts say this has had a dual effect: on one hand, … Read more

Advancements in Two-Dimensional Semiconductor Infrared Sensing by Professor Zou Xuming’s Team at Hunan University

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Advancements in Two-Dimensional Semiconductor Infrared Sensing by Professor Zou Xuming's Team at Hunan University

Infrared detection technology and autonomous driving vision systems are core areas of modern information perception, facing long-standing performance bottlenecks in fundamental devices. In the field of infrared detection, the challenge of balancing dark current suppression and room temperature operation limits the sensitivity and practical application of detectors. In the autonomous driving sector, issues such as … Read more

New Methods for Quantum Computers in Nature Nanotechnology!

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New Methods for Quantum Computers in Nature Nanotechnology!

To fully leverage the potential of quantum computing, error correction must be completed before errors occur. With enhanced connectivity between quantum bits, the redundancy and error rate requirements for achieving fault-tolerant quantum computing can be relatively reduced. Even so, the required redundancy will quickly push the number of quantum bits into the millions. Considering the … Read more

Technical Implementation Approaches for Semiconductor Tunable Lasers

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Technical Implementation Approaches for Semiconductor Tunable Lasers

Abbreviations Used in This Article (1) DFB：Distributed Feedback Laser(分布式反馈激光器)。It provides feedback through an integrated Bragg grating (a periodically modulated refractive index structure), achieving single longitudinal mode laser output with narrow linewidth and high wavelength stability, widely used in optical communication and sensing fields. (2) DBR：Distributed Bragg Reflector Laser(分布式布拉格反射器激光器)。Similar to DFB but with a different structure, … Read more

Detailed Explanation of Semiconductor Chip Packaging and Testing Process

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Detailed Explanation of Semiconductor Chip Packaging and Testing Process

The chip packaging testing phase aims to process wafers that meet quality standards through precise cutting, wire bonding, and encapsulation processes to ensure electrical connections between the chip’s internal circuits and external devices, providing necessary mechanical and physical protection for the chip. Testing tools are used to conduct comprehensive and rigorous functional and performance testing … Read more

Xiaomi’s Self-Developed SoC ‘Xuanjie O1’ Specifications Remain a Mystery, Successfully Taped Out 3nm Chip Last Year

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Xiaomi's Self-Developed SoC 'Xuanjie O1' Specifications Remain a Mystery, Successfully Taped Out 3nm Chip Last Year

Recently, it was officially announced that Xiaomi’s self-developed mobile SoC chip has been named “Xuanjie O1” and will be released in late May. This sudden emergence of a self-developed chip has surprised many, and Lei Jun specifically emphasized that this chip is designed and developed independently by Xiaomi. Xiaomi has done an excellent job of … Read more

Comprehensive Analysis of Chip Fabrication Costs (90nm to 5nm)

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Comprehensive Analysis of Chip Fabrication Costs (90nm to 5nm)

Today, let’s dive into some hardcore content! 🔥 With the help of this chip fabrication cost evolution chart, we will understand how chip manufacturing has been “spending money like water” from 90nm to 5nm. Whether you are a newly minted electronic engineer or a chip investment analysis enthusiast, after reading this, you will confidently say: … Read more