Power Grid Design for Advanced SoCs (TechInsights Analysis Report, January 21, 2025, Author: Tom Dillinger)IntroductionThe development of advanced SoC chip design requires extensive upfront project planning, from market research to technology selection, engineering resource allocation, and the EDA methods employed. A key aspect of this planning work is the implementation of the power/ground distribution network … Read more
As the applications of SoC and FPGA continue to expand in artificial intelligence, automotive electronics, 5G communications, and edge computing, the design complexity of the Power Distribution Network (PDN, Power Distribution Network) has significantly increased. The requirements for multiple voltage rails, transient response, and strict voltage accuracy have made power design not just a peripheral … Read more
Literature from IMEC, published in 2022, focuses on the impact of BSPDN on PPAT.The front end (FEOL) is an active driver of chip power/performance/area (PPA). As scaling approaches the physical limits of semiconductor devices, the back end (BEOL)/middle end (MEOL)/packaging becomes increasingly important for PPA improvements in chips/systems. At 2nm and below, BSPDN back interconnects … Read more
This literature is from IMEC, published in 2022, focusing on the impact of BSPDN on the study of PPAT.The front end (FEOL) is an active driver of chip power/performance/area (PPA). As scaling approaches the physical limits of semiconductor devices, the back end (BEOL)/middle end (MEOL)/packaging becomes increasingly important for PPA improvements in chips/systems. At 2nm … Read more