Low power design has always been a top priority in chip design. The low power technologies adopted by Jingxin SoC training camp include: 1. Clk gating, turning off the clock signals of non-working modules; 2. Power gating, turning off the power of non-working modules; Power gating is more power-efficient than Clk gating because it eliminates … Read more
Low Power Design Techniques: Power Gating and Isolation Cells Previously, we discussed the Multi Vdd technology and Power Gating technology in low power design: Low Power Design Techniques – Multi VDD Low Power Design Techniques – Power/Ground Gating – Power Switching Cell In the introduction of Power Gating, we detailed the Power Switching Cell; here … Read more
Cassie Ren, an architecture expert at Fuzhuo Microelectronics, graduated from the National University of Singapore and has extensive experience in low power chip design and information security, having previously worked at Realtek Semiconductor in Singapore. Background From the relevant policies being introduced, it is clear that the autonomous driving industry is a key area currently … Read more
In the power-off module, it may be required for the register to latch the data before shutdown or to restore the latched data after the power is turned on, which requires a special unit called the Retention Register. The retention register has two sets of registers: the Main Register and the shadow register, where the … Read more
Looking at today’s applications, whether in the Internet of Things, consumer mobile devices, or various devices that can connect to wall outlets, including servers, low power consumption has become a differentiating factor and a necessary condition for product success (as noted by techsugar). Written by: Brian Bailey Translated by: Editorial Team Advancements in mobile technology … Read more
Low-power mechanisms are crucial for processors. This article provides an overview of low-power technologies for processors. For processors, while we pay great attention to their clock frequency and performance, one undeniable fact is that processors spend the vast majority of their time in standby or sleep mode. For example, the smartphones we use daily are … Read more
~ Reply the following keywords to see more IC design tutorials ~ Currently supportedkeywords include: Innovus ICC or IC Compiler DC or Design Compiler PT or PrimeTime User Guide or UG Leda VCS Formality Process Node Low Power CTS vim or gvim … Low power design has always been an important aspect of digital IC … Read more
Source: China Mobile OneNET (ID: CMCC-OneNET) Organized and published by the IoT Think Tank Please indicate the source and origin when reprinting —— [Introduction] —— This article proposes some low power design methodologies for IoT terminals based on the low power requirements of the IoT and certain business scenarios, and lists application scenarios and corresponding … Read more
In the early stages of IC design, the main parameters of concern were performance (timing) and area. EDA tools minimized area while meeting performance requirements. At this time, power consumption was not a major concern. Because CMOS technology exhibits relatively low power consumption at lower clock frequencies, leakage current can be negligible. However, as transistor … Read more
Scan the QR code with WeChat or search for “Digital Integrated Circuit Design and EDA Tutorial” to follow our official account, surprises await you ^_^ This section introduces resource sharing in low power design strategies. Applying this method in code design can reduce system area and power consumption. Of course, some logic synthesis tools may … Read more