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This year,L4 RoboTaxi and L3 conditional autonomous driving have significantly accelerated their commercialization progress. Extreme safety is their common requirement, which also places extreme demands on LiDAR technology.
In April, Didi Autonomous Driving and GAC Aion jointly launched the mass-producedL4 model, which is equipped with 33 sensors around the roof and body, especially LiDAR, with a total of 10 units. In July, the ultra-luxurySUV Zeekr 9X held a technology conference, officially announcing its intelligent driving assistance solution withL3 level capabilities, equipped with 5 LiDAR units, with the main LiDAR exceeding 500 lines.
From a technical perspective,L3/L4 requires higher perception precision and distance compared toL2, which explains the high line count trend required for LiDAR inL3 and L4.
How to achieve high line counts? By combining Sony’s technology, Suoteng Juchuang’s technology, and cutting-edge research papers, we find that the answer is: SPAD-SoC.
SPAD and CMOS are isomorphic and easy to integrate with high line counts
Typical SPAD chip
Image source: Paper “A reconfigurable 3-D stacked SPAD imager with In-pixel histogramming for flash LIDAR or high-speed time-of-flight imaging. IEEE J Solid-State Circuits, 2019, 54“
The structure of the camera’s CMOS is actually quite similar to that of LiDAR’s SPAD, both being pixel arrays with logic circuits. The camera’s CMOS adds column gain, sampling with ADC, while SPAD mainly uses TDC, which is a time-to-digital converter. The pixels also operate on the principle of diodes. The processes are also similar, SPAD can easily achieve 1080, 2160, 4K, 8K or even higher resolutions, resulting in a very high vertical line count for LiDAR. In contrast, using the SiPM solution cannot achieve this.
This is also why SPAD LiDAR is digital and has high line counts, it is simply a more advanced “ 3D digital camera“. Therefore, digital LiDAR and cameras are isomorphic, making them compatible and easy to integrate.
On the left is the VCSEL array drive and control, on the right is the SPAD array and logic. Image source: Paper “A dToF Ranging Sensor with Accurate Photon Detector Measurements for LiDAR Applications“. After TDC processing, it can output a histogram, i.e., Histogram
SPAD and SoC combined, with superior performance
Above is the output format of Sony’s IMX479, which is consistent with the output format of IMX459, still three types, including distance mode, echo mode, and histogram, but the gray bit width is reduced to 12 bits. Suoteng Juchuang’s chip adds a 4 core APU, dual-core MCU, and on-chip memory units, further enhancing integration.
Image source: Paper “A 256×256 LiDAR imaging system based on a 200mW SPAD-based SoC with Micro-lens Array and Light-Weight RGB-guide Depth Completion Neural Network“
The digital processing part in the above image is usually completed by FPGA, but Suoteng Juchuang has integrated this part with the SPAD array.
Why do this? Because high line count LiDAR has high bandwidth requirements, 520 line LiDAR is equivalent to traditional 20 million pixels, and there is currently no corresponding 20 million pixel serial and deserialization chip; if there is in the future, it will inevitably be expensive. Moreover, the TDC of LiDAR is a picosecond-level device, with a picosecond being one trillionth of a second. The transmission and exchange of large-capacity high-speed data require close proximity to avoid driving and signal quality issues. The best approach is to shorten the physical distance, i.e., integrating the SPAD array and SoC on a single chip, with a physical distance on the micrometer scale.
Suoteng Juchuang’s data processing is also integrated with the SPAD array, which not only reduces the cost of the computing system but also improves data transmission efficiency.
Calculating the point cloud and depth map of LiDAR involves many nonlinear operations, which cannot be accelerated by AI accelerators; they can only accelerate matrix multiplication and accumulation. These nonlinear operations will automatically be processed by the most flexible CPU, which increases the burden on the CPU, while Suoteng Juchuang’s design does not rely on external computing units, and due to the close physical distance, performance is better.
Integrating the SPAD pixel array with large-scale SoC logic circuits to directly output point cloud and depth map data is also very challenging in chip manufacturing technology. Small-scale integrations, such as some TDC or OR tree logic integrations, are not difficult, but integrating MCU, APU, and achieving a frequency of 1 GHz is extremely challenging. Globally, only Suoteng Juchuang has achieved this; even Sony has not. Suoteng Juchuang has not only achieved the industry’s first integration of APU, MCU into SPAD, but also for the first time introduced RISC-V as the architecture for APU and MCU. With this technological strength, Suoteng Juchuang has become a leader in the chip industry.
Why use RISC-V? In traditional designs, hardware accelerators are generally mounted to the internal bus of the SoC via memory mapping, and the CPU controls their operating modes by issuing Load/Store instructions to read and write the configuration registers inside the hardware accelerators. In this architecture, the CPU and hardware accelerators have a loosely coupled relationship, with the hardware accelerators operating under the drive of their internal configuration registers. The emergence of the RISC-V instruction set architecture provides a good platform for domain-specific architecture design (Domain Specific Architecture, DSA). By customizing instruction extensions, hardware accelerators can be embedded into the CPU microarchitecture pipeline as an execution unit, achieving tighter coupling with the CPU. In this architecture, hardware accelerators can directly exchange data with the register file in the CPU and operate under the drive of the pipeline and instruction flow, greatly improving the data interaction efficiency between the CPU and hardware accelerators.
Suoteng Juchuang’s self-developed SPAD-SoC innovatively introduces RISC-V architecture
Source: Suoteng Juchuang
RISC-V instruction set architecture adopts a modular design, requiring only the microarchitecture to implement the basic integer instruction set (RV32I/RV64I), while the remaining instruction sets are optional extensions. The extensions approved by RISC-V are called standard extensions, such as the compressed instruction extension (C), multiplication and division instruction extension (M), floating-point instruction extension (F/D), etc., all of which have stable instruction encoding.
The future belongs to SPAD and high line counts
Thanks to this chip technology, Suoteng Juchuang EM4 can achieve up to 2160 lines, with a minimum of 520 lines. Just on July 9, at the launch of Geely’s Haohan-S architecture and Zeekr 9X technology, the Zeekr 9X made a stunning appearance. As the flagship model representing the highest standard of the Haohan intelligent driving assistance system, the Zeekr 9X adopts the industry’s only 5 LiDAR solution, all of which are digital radars. The customized RoboSense Suoteng Juchuang 520 line digital LiDAR is currently the highest performance mass-produced automotive-grade LiDAR product, unmatched by any other, leading the industry by at least a year and a half to two years. It is reported that several other L3 models equipped with EM4 will be released within the year.
Suoteng Juchuang EM4 point cloud in road testing, toll station scenarios, suppressing high reflectivity expansion effects
Source: Suoteng Juchuang
EM4’s leadership comes not only from the SPAD-SoC chip but also from the complete digital LiDAR architecture and signal processing algorithms developed around this chip, which have matured. Based on actual measured point clouds and published materials, Suoteng Juchuang has solved key issues such as high reflectivity expansion, ambient light interference, dirt occlusion, and rain and snow noise that SPAD must overcome, achieving standards for large-scale mass production.
In the process of high line count LiDAR development, Suoteng Juchuang, with its strong chip development capabilities and precise judgment of chip technology, has not only led the mass production of SPAD-SoC but also promoted the mass production of ultra-high line count LiDAR through the EM platform products, achieving a breakthrough of “thousand lines” for LiDAR, providing solid technical support for the safe and efficient large-scale application of L3 and L4 autonomous driving.
Through the detailed technical and case analysis above, we not only obtain an answer: the solution for achieving high line counts in LiDAR is the evolution from traditional analog architecture to SPAD-based digital architecture, but we also recognize that SPAD-SoC is the superior chip solution among them. At the same time, the isomorphic characteristics of SPAD and CMOS provide great convenience for the integration of digital LiDAR and cameras, which not only greatly enhances the multi-sensor fusion effect of L3/L4 but also promotes the development of machine vision system technology from multi-sensor fusion to integrated multi-sensor integration. Currently, Suoteng Juchuang, as a leader in this field, has launched a new category of products for integrated multi-sensor integration.
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