Analog IC design has emerged relatively late in China, and there are currently very few mature designs. Most of the chips produced are essentially imitations of products from major international companies like TI, Maxim, LT, etc., achieving Pin to Pin compatibility, with specifications that are basically the same. In short, it follows the replacement principle. Since domestic IC design companies generally do not have their own fabrication plants, they often rely on TSMC, Chartered, and the relatively cheaper CSMC. Therefore, when copying chips from the US and Taiwan, most can only achieve a similar appearance but cannot replicate the intricate details, as some special circuits require specific device structures and doping concentrations. Altering these conditions can be costly and risky for smaller companies. Thus, I would like to share some immature opinions and experiences regarding the current state of analog IC design in China, and I welcome corrections from experts.
First of all, when designing chips, running Corner simulations is probably the most familiar task for everyone. SS, FS, TT, etc., involve transistors, resistors, high voltage, and low voltage. If you only use the Corner tools under Cadence, it may not be sufficient, as I need various combinations of Corners. Current and voltage also need to have certain margins. For example, if the typical current value is 8uA and the offset is 1uA, then I also need to run the 6uA and 10uA corners. This way, when running a not-so-large sub-circuit module, I can have on the order of 3 to 7 to 10 times the number of Corners. Although such simulations are conservative, they will make our system appear more Robust for the future performance of the Wafer. The solution is to write an Ocean Script to automate the process, allowing all Corners (for small circuits) to be completed over a weekend. Then, when you come in on Monday, you will find that the values of your circuit under certain temperatures and conditions are unacceptable, and you must modify the circuit!
Next is the layout. Do not expect all current mirrors to be perfectly accurate, or that all input transistors have no offset. This is certainly impossible; the key is how to minimize it. In addition to intentionally increasing W or L in circuit design, you also need to calculate how much offset will cause your circuit to completely not work. In layout design, cross intersections have become common. However, saving area seems to contradict the use of Dummy devices, making it difficult to choose. One method is to place a 20/3 MOSFET next to a 20/0.5 Dummy, so they do not interfere with each other! Additionally, there are other considerations, such as the fact that OSC is an active component, not only affecting the metal layers but also being quite disruptive to the Sub, often disturbing nearby components like the quiet Current bias and OTA. Some resistors need to be both proportionally accurate and have precise absolute values, so you have to allocate the best areas on the chip for them to minimize the stress during slicing.MPW is very cheap, so do not skimp on area; add more Pads to ensure that each circuit module can operate independently even if the front and back circuit units do not work, as you never know which module might fail. You must be well-prepared to avoid having all modules turn into bricks just because one Bandgap fails! Additionally, always add test keys on the Scribe line, including Full mask, as we never complain about having too much measurement data for a particular process.Full Mask can have many versions, differing by only one layer of metal, allowing us to test and find the optimal design solutions for each sub-circuit. For the next tape-out, we only need to change one layer of mask to achieve the optimal combination. Isn’t that attractive?
The Wafer is back! So exciting! Is it a circuit or a stone? We will know once we test it on the probe station.HP 4155/6 is an essential tool; to be precise, you need the right instruments. Well, most DC parameters are acceptable, but the long connections significantly affect parasitic inductance and resistance. Should we go directly to the Package? Haha, we are small customers, and they hardly pay attention to us, let alone ST. Generally, it takes at least half a month for them to process it. If your chip is relatively large and has peripheral circuits, the best solution is to do a COB! Directly thin the Wafer (to prepare for packaging), cut off a 1/3 piece, slice it, Bonding it to the PCB, pour on black glue, and voila, solder on the peripheral circuits, and you have a working phone! This only takes 2-3 days. The remaining 2/3 can be sent to CD for packaging. During this time, we can collect a lot of data, and if the bonding is done well, the results will be very close to those of the packaged version.Full Mask should return with more than one piece, so we can send the other pieces to the testing factory to measure all the wafers and see how the statistics look. Of course, the testing program must be prepared in advance, and it is best if you are familiar with 6800 and C language!
Before testing, be sure to create a table with as much detail as possible; during the testing process, each COB must be labeled and correspond to the measurement data for future reference to determine whether the issue lies with the chip or the setup. Then, process the data; you can use Excel, right? Provide statistical curves for testing to facilitate future design references.
ESD is a top priority in design; otherwise, you might think you are haunted by evil spirits, as yesterday’s results can differ greatly from today’s, and even results from an hour ago may vary. Unfortunately, you need to contact an ESD testing factory to see how many volts your chip can withstand in mechanical and human modes! If it fails, you must make changes next time, as there is no room for negotiation.
EMC depends on what you are selling, and it is particularly strict for mobile phones. If you are selling domestically, it is generally acceptable.
ISO9000 certification is a must; if you cannot pass the documentation, it reflects poorly on your intelligence.
