The chip industry has recently been hit with concerning news: data from electronic design automation tools released by Siemens indicates that the current success rate for first tape-outs has plummeted to an unprecedented low of 14%. Just two years ago, this figure was around 24%, meaning the failure rate has surged by ten percentage points in a mere two years. Industry experts point out that such a drastic decline is extremely rare in the history of semiconductor development, reflecting that current chip design is facing systemic challenges.
The tape-out process is critical for chip design companies. In simple terms, it involves sending the designed chip solution to a wafer fab for trial production to verify whether the design meets standards. However, this process is becoming a gamble—eight out of ten companies fail on their first attempt. Even more severe is that a single failure can cost up to tens of millions, which is catastrophic for small to medium-sized design firms. Analysts have calculated that if a medium-sized chip design company experiences two consecutive tape-out failures, it could easily exhaust its entire annual R&D budget.
A deeper analysis of this phenomenon reveals that multiple factors are at play. The complexity of modern chips has increased dramatically; products like mobile processors need to integrate multiple functional units such as CPU, GPU, and NPU, while also balancing power consumption and heat dissipation. AMD’s Bulldozer architecture and Qualcomm’s Snapdragon 810 have both stumbled at this stage.
Sometimes, chip failures are not due to functional defects, but rather because the operating speed is 10% slower than expected, or power consumption is 10% higher, making such products uncompetitive in the market. A chip designer, who wished to remain anonymous, revealed: “Designing a chip now feels like walking a tightrope, balancing a dozen key parameters, and a slight misstep can lead to total failure.”
The issue of verification cycles is also prominent. With the growing demand for customized chips, the design verification for specific algorithms and application scenarios has become exceptionally cumbersome. However, the market’s window of opportunity for companies is continuously shrinking, and this time pressure further amplifies the risk of errors. A technical supervisor at TSMC stated: “Five years ago, a chip project could have an 18-month verification cycle; now clients often demand completion in just 9 months.”
“Even more concerning is that as the process technology advances to the 2nm node, the costs of tape-outs are rising sharply, while yield improvements are proving difficult, leading companies into a vicious cycle of ‘the more tape-outs, the more losses.’ Data shows that the cost of tape-outs using 5nm technology is already more than double that of 7nm technology.
In the face of such challenges, a new trend is emerging in the industry. More and more companies are choosing to collaborate with specialized ASIC firms to tackle challenges through more refined professional division of labor. The world’s third-largest chip design company, MediaTek, recently announced that it will outsource part of the design verification work for high-end chips to specialized teams. Additionally, some innovative companies are beginning to experiment with ‘virtual tape-out’ technology, using digital twin methods for more thorough simulation verification before tape-outs. ARM’s latest verification platform claims to improve tape-out success rates by 30%.
This winter in the chip industry may be reshaping the entire ecosystem of the supply chain. In the long run, this could prompt the industry to establish more comprehensive design specifications and more mature collaboration mechanisms. However, for now, how to survive this challenging period of high tape-out failure rates remains a pressing reality for every chip company. As one industry observer put it: “The current chip industry is like a ship sailing in a storm, needing to navigate the immediate turbulent waves while also planning for future routes.”