On June 2, Chip Ranking reported that the success rate of chip tape-outs has dropped to a historical low!
According to Siemens EDA data,the success rate of first-time chip design tape-outs has fallen to 14%, a significant decrease from 24% two years ago. Eight out of ten companies failed their first tape-out.
The reasons stem from increased chip complexity and changes in corporate development models, suggesting that future specialization and outsourcing to ASIC companies may become a trend.
The Most Severe Challenge in the Semiconductor Industry in the Last Decade
The tape-out of chips, regarded as the “college entrance examination” of the semiconductor industry, is facing unprecedented challenges.
According to data from Siemens Electronic Design Automation (EDA) tools, the success rate of first-time tape-outs for chips has dropped to14%, nearly halving from 24% two years ago, meaning that only one out of ten companies can successfully “pass” on their first tape-out.
This figure far exceeds the drop from 30% to 26% in 2018, marking the most severe “success rate crisis” in the semiconductor industry in the past decade.
The cost of tape-out failures is astronomical: a single tape-out can cost anywhere from tens of millions to hundreds of millions, and failure not only means wasted funds but can also cause companies to miss a market window of 6-12 months.
Four Major Factors: Complexity, Customization, and the “Acceleration Trap”
The sharp decline in the success rate of chip tape-outs is the result of multiple technological transformations and clashes in business logic:
1. The “stacking” complexity of chip architecture As Moore’s Law slows, multi-chip modules (MCM) have become the mainstream choice. An advanced server chip may integrate 5nm computing cores, 14nm storage units, and 28nm interface modules, requiring coordination among multiple foundries like TSMC, Samsung, and Intel. This “splicing” design not only increases the difficulty of layout integration but also exponentially raises issues such as signal delay and thermal management.
2. The “one size fits all” dilemma of customized chips AI, autonomous driving, and other scenarios have generated massive demand for customization. For instance, deep learning inference chips need to optimize instruction sets for specific neural network architectures, requiring a “from scratch” approach from architecture design to validation. A certain AI chip company revealed that its customized chip validation use cases exceed 1 billion, five times more than general-purpose chips, while traditional EDA tools struggle to handle such complex scenario coverage.
3. The “acceleration trap” of compressed development cycles To cope with market competition, chip development cycles have been compressed from 18 months to 12 months or even shorter. Companies often simplify critical validation steps to meet deadlines—one FPGA manufacturer, in a rush to capture the AI accelerator card market, skipped some timing validations, resulting in a chip frequency 20% lower than expected after tape-out, ultimately forcing a redesign and delaying the market launch by a year.
4. The “generational gap” between AI computing demand and validation capabilities The parameters of AI models have surged from billions to trillions, leading to an explosive increase in chip computing demands. However, development tools have not upgraded in sync: engineers still need to debug complex architectures of 2025 using validation platforms from the 2010s, akin to “using an abacus to calculate aerospace trajectories.” Semiconductor engineering editor Brian Bailey pointed out: “AI is pushing chip advancements at ‘rocket speed,’ but validation productivity remains stuck in the ‘steam age.'”
Three, Behind the Drop to 14%: Systemic Challenges in the Semiconductor Supply Chain
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Bottlenecks in advanced process yields: Mass production of 2nm/3nm processes is challenging, with TSMC’s 2nm yield at 60%, Samsung’s 3nm yield between 20%-60%, and Intel’s first batch yield below 30%, requiring customers to pay high assurance fees.
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Chiplet technology risks: While multi-chip packaging avoids process risks, overall yield drops sharply as components increase (for example, a combination of 10 chips with 95% yield results in an overall yield of only 60%). In 2024, a certain chip faced over 40% board scrap rate due to a single component defect, resulting in losses exceeding $500 million.
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Trust crisis in the supply chain: In Q1 2025, disputes over tape-outs increased by 78% year-on-year, with the division of responsibilities between design and manufacturing becoming a focal point.
Industry breakthroughs focus on four areas: introducing AI-assisted validation at the design end (e.g., Synopsys platform shortening cycles by 40%); improving yields above 90% at the manufacturing end through TSMC’s “CoWoS packaging + 2nm” and Intel’s Foveros technology; promoting small and medium enterprises to outsource to ASIC manufacturers (increasing first tape-out success rates to 35%) and encouraging leading companies to share data; and at the talent end, universities establishing interdisciplinary programs and companies implementing job rotation systems to cultivate versatile talents. This crisis is forcing the industry to transition to customization; only by breaking the “lone wolf” approach and building a collaborative system of technology, talent, and ecology can the industry achieve upgrades.
Four, RISC-V 2030 Research Report
Chip Ranking is drafting the “RISC-V 2030 Research Report” white paper, which is of great significance, and sincerely invites companies to join in building the ecosystem. RISC-V is key for China to break the chip technology blockade and achieve self-control, potentially reducing R&D costs. Interested parties can add WeChat 105887 (please note RISC-V) to build the future together.
*Disclaimer: This article is original by the author. The content reflects the author’s personal views, and the reprint by LuKe Verification is solely to convey a different perspective, not representing LuKe Verification’s endorsement or support of this view. If there are any objections, please contact LuKe Verification.