On June 2, according to data from Siemens Electronic Design Automation (EDA) tools, the success rate of first tape-out for chip designs has dropped to a historic low of 14%, a significant decrease from 24% two years ago. This means that eight out of ten chip design companies will encounter failure during their first tape-out.
Modern chip design is becoming increasingly complex, with a growing adoption of multi-chip components, which often need to be produced at different process nodes. For example, in advanced server chips, the computing cores may use a 5nm process for higher performance and lower power consumption, while the memory units may utilize a more mature 14nm process to ensure cost-effectiveness and stability. This complexity increases the difficulty of design and manufacturing.
To maintain market competitiveness, companies need to launch more products in a shorter time frame, leading many chip firms to compress design and verification times, and even simplify processes in critical areas. Potential issues in design may not be identified and resolved in a timely manner, increasing the risk of tape-out failure.
The rapid development of artificial intelligence has placed extremely high demands on the computational capabilities of semiconductor chips. AI applications require chips to provide greater computing power, but current development and verification productivity has not seen corresponding breakthroughs. This forces chip design teams to deliver more complex designs within limited timeframes, further increasing the risk of first tape-out failure.
Tape-out is a critical test for chip design, akin to a matter of life and death. Once a tape-out fails, not only are the millions invested in R&D wasted, but it may also result in missed market opportunities.