Methods Related to Low Power:
1. Clock Gating
The RTL code must follow the low power style, and there should be at least three or four registers after the enable signal for the tool to synthesize it into a clock gate.
2. Lower VT
3. Gate Level Power Optimization
4. In terms of architecture, this method can significantly reduce power consumption.
Advanced Low Power Techniques:
MV: For modules with high frequency requirements (CPU, GPU), the voltage will be boosted to 1.2V, which increases performance, while normal modules will use standard voltage.
MTCMOS: Some modules can be shut down and awakened when needed. Additionally, there is OFF+RR, which allows for quick recovery of previously retained values upon waking.
Standby: Uses a low voltage of 0.6V to maintain some basic functions, and when high performance is needed, it is responsible for waking up other functions. Generally, a small CPU is included within the 0.6V range.
DVS/DVFS/AVS/AVFS: Dynamic adjustments of voltage and frequency. Dynamic refers to several levels (0.9V, 1.0V, 1.1V three levels, with signoff at 1.1V), while Adaptive refers to self-adjusting voltage (AMD, Intel).
VTCMOS: Applies a bias voltage to the well to reduce leakage current. This process is commonly used today.
Challenges of Low Power Techniques:
System: Increased complexity and area, requiring additional consideration of hardware and software, which affects functionality.
Verification: Special cell verification is troublesome, prone to X-state transmission, requiring extra attention to state, and the process library must support it, with the reset process also needing attention.
Implementation: Clock tree planning is difficult, DFT coverage decreases, and costs increase.
Signoff: Both low power and normal parts need verification. Power switches added to the power plan can lead to greater IR drop reductions.