Introduction to Semiconductor Materials: From Crystal Structure to Wafer Birth, Unveiling the ‘Foundational Manufacturing Techniques’ of Chips

In the chip industry, semiconductor materials are undoubtedly the ‘foundation’, with silicon materials being the core. A qualified wafer undergoes a long journey from crystal structure design to multiple precision processing steps. Today, we will systematically outline the key knowledge of semiconductor materials and understand the complete manufacturing logic from silicon raw materials to wafers.

1. Basic Understanding: The ‘Structural Code’ of Semiconductor Crystals

To understand semiconductor materials, we must first discuss their ‘microscopic framework’—the crystal structure.

1. Single Crystal vs. Polycrystal: The Core Difference Lies in ‘Arrangement’

• Single Crystal: In a single crystal, atoms are arranged in a regular, periodic pattern throughout the material (e.g., silicon single crystal), exhibiting excellent electrical properties and serving as the core raw material for semiconductor chips.
• Polycrystal: Composed of numerous small single crystals stacked randomly (e.g., most metals, electronic ceramics), due to the disordered orientation of grains, the macroscopic properties are mostly isotropic, making them unsuitable for direct chip manufacturing.

2. Typical Structure: The ‘Diamond Configuration’ of Semiconductor Silicon

Silicon, germanium, and other semiconductor materials all possess adiamond structure, which can be viewed as two face-centered cubic unit cells offset along the body diagonal by 1/4 of the length, a structure that determines their unique electrical conductivity characteristics.

3. Crystal Planes and Directions: The Universal Language for ‘Positioning’ Crystals

Crystals exhibit anisotropy, with significant differences in physical properties in different directions, thus requiring the use ofMiller Indices to denote crystal planes and directions:

• Crystal Direction Indices [u v w]: A coordinate system is established with the lattice points as the origin, taking the coordinates of the nearest lattice point on the desired crystal direction line, converting them to the smallest integers and enclosing them in square brackets, representing all parallel and directionally consistent crystal directions.
• Crystal Plane Indices (h k l): The reciprocals of the intercepts of the crystal plane on the coordinate axes are taken, converted to coprime integer ratios, and enclosed in parentheses, representing all mutually parallel crystal planes (if the intercept is negative, a ‘-‘ is added to the index; if parallel to the axis, the intercept is ∞, and the reciprocal is 0).

2. Key Influences: ‘Defects and Impurities’ in Crystals

Even minute amounts of defects and impurities can directly determine the performance of semiconductor materials, which is the core reason for ‘controlling impurities’ and ‘controlling defects’ in semiconductor manufacturing.

1. Crystal Defects: Four Types Based on Spatial Configuration

• Point Defects: Centered around vacancies, interstitial atoms, and impurity atoms, these are distortion regions within 1 to several lattice constants, representing the most microscopic type of defect.
• Line Defects: Structural deviations in one-dimensional directions, the most typical being ‘dislocations’, which can affect the mechanical and electrical properties of the crystal.
• Surface Defects: Such as ‘stacking faults’, formed due to disordered atomic stacking sequences, existing only in localized areas while surrounding atoms remain regularly arranged.
• Volume Defects: Such as ‘inclusions’, which form when impurities exceed the solubility of the crystal, directly damaging the integrity of the crystal.

2. Doping Control: Determining the ‘Conductivity Type’ of Semiconductors

By actively introducing impurities, the electrical characteristics of semiconductors can be altered, primarily divided into two categories:

• Donor Impurities (n-type impurities): For example, doping silicon with phosphorus, where phosphorus atoms occupy silicon atom positions, forming positive charge centers and excess valence electrons, allowing the semiconductor to conduct primarily through electrons (n-type semiconductor).
• Acceptor Impurities (p-type impurities): For example, doping silicon with boron, where boron atoms occupy silicon atom positions, forming negative charge centers and excess vacancies (holes), allowing the semiconductor to conduct primarily through holes (p-type semiconductor).

3. Core Process: The ‘Transformation’ from Polycrystalline Silicon to Monocrystalline Silicon

The mainstream semiconductor silicon material is monocrystalline silicon, which is produced through two major stages: ‘polycrystalline silicon synthesis → monocrystalline silicon growth’, with 300mm (12-inch) wafer technology becoming the industry standard.

1. Polycrystalline Silicon Preparation: From Raw Materials to High-Purity Silicon

Using the ‘trichlorosilane method’, the core reaction occurs in three steps:

1. High-Temperature Chlorination: Low-purity silicon reacts with HCl to produce low-purity trichlorosilane (Si + 3HCl → SiHCl₃ + H₂);
2. Purification: The low-purity trichlorosilane is refined to obtain high-purity trichlorosilane;
3. High-Temperature Hydrogen Reduction: High-purity trichlorosilane reacts with hydrogen to produce high-purity silicon (SiHCl₃ + H₂ → Si + 3HCl).

2. Monocrystalline Silicon Growth: 85% Use the ‘Czochralski Method (CZ Method)’

(1) Monocrystalline Furnace: The ‘Core Equipment’ for Growth

Composed of four major systems, requiring extremely high vacuum and gas purity (vacuum ≥ 5 Torr, inert gas purity ≥ 99.9999%):

• Furnace Body: Includes the furnace chamber (temperature control and heat dissipation), seed crystal shaft (driving seed crystal movement), quartz crucible (holding silicon material), and doping spoon (for adding impurities);
• Mechanical Transmission System: Controls the rotation and elevation of the seed crystal and crucible;
• Heating Temperature Control System: Maintains the melting temperature of silicon material (approximately 1420°C);
• Gas Delivery System: Introduces inert gas to prevent oxidation of silicon material.

(2) Five Steps of Growth: Precise Control of Each Step

1. Preparation: Select high-purity polycrystalline silicon (cleaned with hydrofluoric acid), choose defect-free seed crystals with matching crystal orientations (cleaned and reserved), prepare impurities according to conductivity type and clean;
2. Loading into Furnace: After crushing polycrystalline silicon, load it into the quartz crucible, fix the seed crystal on the seed crystal shaft, evacuate the furnace and fill it with inert gas, and check for leakage rates;
3. Melting Silicon: Use high-frequency coils or current heaters to heat and melt polycrystalline silicon and impurities at 1420°C;
4. Pulling Crystals: The core step, divided into five sub-steps:

• Seed Crystal Introduction: Cool down to slightly below 1420°C, lower the seed crystal to a few millimeters above the liquid surface and preheat for 2-3 minutes before contacting the molten silicon;
• Necking: Increase temperature, rotate the seed crystal upward to form a thin crystal with a diameter of 0.5-0.7 cm, eliminating original defects of the seed crystal;
• Shoulder Formation: Slow down the pulling speed and cool down to increase the crystal diameter to the target size;
• Constant Diameter Growth: Fine-tune the temperature, maintain stable pulling speed and temperature to grow the crystal at a fixed diameter;
• Finishing: Increase temperature and speed, reduce the diameter of the crystal rod to form a tapered tail, avoiding defects caused by cooling;

Testing: Test the performance of monocrystalline silicon, including physical properties (appearance, crystal orientation, diameter), defects (dislocations, inclusions, etc.), and electrical parameters (conductivity type, non-equilibrium carriers, resistivity).

4. The Final Step: ‘Precision Processing’ from Crystal Rod to Wafer

The grown monocrystalline silicon rod must undergo six processing steps to become a ‘wafer’ that meets chip manufacturing requirements:

1. Shaping: ‘Molding’ the Crystal Rod

• Cutting and Segmenting: Remove the seed crystal, shoulder, tail, and parts with diameter/resistivity/structure that do not meet standards;
• Radial Grinding: Correct the diameter of the crystal rod to meet specifications;
• Reference Plane Grinding: Roll grind along key crystal planes to facilitate subsequent positioning (e.g., P-type <100>, N-type <111> etc.).

2. Slicing: ‘Cutting the Crystal Rod into Wafers’

Using an inner circular cutting machine, determine the thickness, slope, parallelism, and warpage of the wafer, with the process being: fixing the crystal rod → X-ray positioning → slicing → wafer removal → cleaning.

3. Chamfering: Grinding Away ‘Sharp Edges’

Grind away the edges of the wafer to prevent edge breakage, reduce thermal stress damage, and improve the flatness of the epitaxial layer and photoresist at the edges.

4. Grinding: ‘Flattening’ the Wafer

Remove the cutting marks left by slicing, eliminate the surface damage layer, ensuring uniform thickness and improved flatness of the wafer.

5. Polishing: Creating a ‘Smooth Surface’

• Method: The mainstream method is ‘Chemical Mechanical Polishing (CMP)’, which is efficient and provides good surface quality (mechanical polishing is less efficient and consumes more materials);
• Inspection: Use a ‘magic mirror’ (resolution 0.05μm) to check for surface defects and atomic force microscopy to measure roughness (key parameters: TTV thickness variation, TIR height variation sum, FPD maximum distance).

6. Cleaning: ‘Cleaning’ the Wafer

Using the ‘RCA cleaning method’ (mainstream wet chemical cleaning technology), remove residues of polishing agents, grinding materials, and other impurities from the processing, ensuring the wafer is clean.

From the atomic arrangement of the crystal structure to the multiple precision manufacturing processes, the birth of a wafer embodies countless technological wisdom. As the ‘foundation’ of chips, every aspect of semiconductor materials pursues ‘extreme precision’—this is the starting point for the ‘micron-level and even nanometer-level’ precision requirements of the chip industry.

What other aspects of semiconductor manufacturing would you like to learn about? Feel free to leave a comment for discussion!