On September 18, at the Huawei Connect 2025 conference, Huawei’s rotating chairman Xu Zhijun delivered a keynote speech titled “Leading a New Paradigm of AI Infrastructure with Innovative Super Node Interconnection Technology.” In his speech, he reviewed the profound changes in the AI industry over the past year, candidly discussed the impacts and opportunities brought by open-source models like DeepSeek, and reaffirmed Huawei’s strategic determination in the field of computing power.
Xu Zhijun elaborated on how Huawei is building a sustainable and high-performance AI computing foundation through its groundbreaking “super node + cluster” computing architecture and the new “UnifiedBus” interconnection protocol.
He not only announced the detailed roadmap for the Ascend AI chips and Kunpeng general-purpose computing chips over the next three years but also launched several globally leading super node and cluster products, aiming to lead AI infrastructure into a new paradigm and provide solid computing power support for AI development in China and globally.
The following is the full text of Xu Zhijun’s speech:
Ladies and gentlemen, old friends, and new friends, good morning! Welcome to the 2025 Huawei Connect conference. After a year, I am very pleased to meet you again in Shanghai. I believe everyone can feel that the past year has been a memorable one for all AI practitioners and observers. The emergence of DeepSeek has allowed the entire nation to enjoy a joyful AI year, and it has also led many large model trainers to spend countless sleepless nights adjusting training methods to replicate DeepSeek’s results, which has undoubtedly brought us tremendous impact. From the Spring Festival until April 30 this year, through the collaborative efforts of multiple teams, we finally met the basic needs of customers with the inference capabilities of Ascend 910B/910C.
Before diving into today’s specific sharing, please allow me to review last year’s HC, where I mentioned the following points:
First, sustainable intelligence starts with sustainable computing power;
Second, China’s semiconductor manufacturing processes will remain behind for a considerable time;
Third, sustainable computing power can only be based on the chip manufacturing processes that are actually available;
Fourth, artificial intelligence has become the dominant computing power demand, prompting structural changes in computing systems;
Fifth, creating a computing architecture and building a “super node + cluster” computing solution to continuously meet computing power demands.
However, I did not elaborate on the fifth point, which I originally intended to discuss, but my team disagreed. Today, I would like to take this opportunity to complete the task I did not finish last year at HC, which can also be considered as my answer. The theme of my sharing today is: “Leading a New Paradigm of AI Infrastructure with Innovative Super Node Interconnection Technology,” which also answers the fifth point mentioned at last year’s HC: how to create a computing architecture and build a “super node + cluster” computing solution to continuously meet computing power demands.
Before expanding on today’s theme, let’s return to the impact of DeepSeek on the industry and Huawei. After the open-sourcing of DeepSeek, our customers pointed out many issues regarding Huawei’s Ascend development, filled with expectations, and have continuously provided us with suggestions. Therefore, after thorough internal discussions and reaching a consensus, we held the Ascend Industry Summit on August 5, 2025, in Beijing, where I represented Huawei to respond. Some of you attended, while others may not have. Today, I would like to take this opportunity to report on the main decisions made. There are four key points:
1. Huawei insists on monetizing Ascend hardware;
2. The CANN compiler and virtual instruction set interface will be open, and all other software will be open-source. The open-source of CANN based on Ascend 910B/C will be completed by December 31, 2025, with future open-source releases synchronized with product launches;
3. The Mind series application enablement suite and toolchain will be fully open-sourced and completed by December 31, 2025;
4. The openPangu foundational large model will be fully open-sourced.
Now, returning to today’s theme. Although the model created by DeepSeek can significantly reduce computing power demands, to move towards AGI and physical AI, we believe that computing power, which has been crucial in the past, will continue to be key for artificial intelligence in the future, and it is also critical for China’s artificial intelligence.
The foundation of computing power is chips, and Ascend chips are the foundation of Huawei’s AI computing power strategy. Since the release of the Ascend 310 chip in 2018, the Ascend 910 chip in 2019, and now the Ascend 910C chip in 2025, along with the large-scale deployment of the Atlas 900 super node, these have become well-known. Over the past few years, customers and partners have had many demands and expectations for Ascend chips. Looking to the future, what is Huawei’s roadmap for chips? This is undoubtedly a topic of general concern and perhaps the most concerning content.
Therefore, today, I will directly introduce the Ascend chips and their roadmap. I can confidently tell everyone that Ascend chips will continue to evolve, building a solid foundation for AI computing power in China and the world.
In the next three years, by 2028, we have developed and planned three series: the Ascend 950 series, which includes two chips: Ascend 950PR and Ascend 950DT, as well as the Ascend 960 and Ascend 970 series, with more specific chips still in planning. Below, I will introduce the four Ascend chips that are about to be launched and have been planned.
We are developing and will soon launch a chip called the Ascend 950 series. First, let me introduce the architecture of the Ascend 950 series chips, where Ascend 950 PR and Ascend 950 DT share the Ascend 950 Die. Compared to the previous generation of Ascend chips, the Ascend 950 has achieved fundamental improvements in several aspects.
First, it adds support for industry-standard low-precision data formats such as FP8/MXFP8/MXFP4, achieving computing power of 1P and 2P, enhancing training efficiency and inference throughput. It also specifically supports Huawei’s self-developed HiF8, which maintains the efficiency of FP8 while achieving precision very close to FP16.
Second, it significantly enhances vector computing power. This is mainly achieved through three aspects: first, increasing the proportion of vector computing power; second, adopting an innovative new homogeneous design that supports both SIMD/SIMT dual programming models, where SIMD can process “large blocks” of vectors like a pipeline, while SIMT is convenient for flexibly handling “fragmented” data; third, reducing the memory access granularity from 512 bytes to 128 bytes, allowing for finer memory access, thus better supporting discrete and non-continuous memory access.
Third, the interconnection bandwidth has increased 2.5 times compared to the Ascend 910C, reaching 2TB/s.
Fourth, considering the different demands for computing power, memory, memory bandwidth, and recommendations during different stages of inference, we have developed two types of HBM: HiBL 1.0 and HiZQ 2.0. Different self-developed HBM combined with the Ascend 950 Die form the chips Ascend 950PR, aimed at prefill and recommendation scenarios, and Ascend 950DT, aimed at decode and training scenarios. Below, I will introduce them separately.
First is our first chip, Ascend 950PR, mainly aimed at the inference prefill stage and recommendation business scenarios. We have found that with the rapid development of agents, the input context is becoming longer, and the first token output stage occupies more computing resources. Additionally, in e-commerce, content platforms, and social media applications, there is a growing demand for recommendation algorithms to have higher accuracy and lower latency, which increases the demand for computing power. The inference prefill stage and recommendation algorithms are both compute-intensive and require high parallel computing capabilities, but their demand for memory access bandwidth is relatively low. Through a hierarchical memory solution, the inference prefill stage and recommendation algorithms do not have high local memory capacity requirements. The Ascend 950PR uses Huawei’s self-developed low-cost HBM, HiBL 1.0, which can significantly reduce the investment in inference prefill stages and recommendation businesses compared to high-performance, high-cost HBM3e/4e.
This chip will be launched in the first quarter of 2026, with the first supported product form being standard cards and super node servers.
Next is the Ascend 950DT, which focuses more on the inference decode stage and training scenarios compared to the Ascend 950PR. Due to the high demands for interconnection bandwidth and memory bandwidth during the inference decode stage and training, we developed HiZQ 2.0, which allows for a memory capacity of 144GB and a memory access bandwidth of 4TB/s. At the same time, the interconnection bandwidth has been increased to 2TB/s. Additionally, it supports FP8/MXFP8/MXFP4/HiF8 data formats.
The Ascend 950DT will be launched in Q4 2026.
The third chip is the Ascend 960, which is in planning. It will double various specifications such as computing power, memory access bandwidth, memory capacity, and the number of interconnection ports compared to the Ascend 950, significantly enhancing performance in training, inference, and other scenarios. It will also support Huawei’s self-developed HiF4 data format, which is currently the industry’s best implementation of 4-bit precision, further improving inference throughput and achieving better inference accuracy than the industry’s FP4 solutions.
The Ascend 960 is scheduled for release in Q4 2027.
Finally, the Ascend 970 is also in planning, with some specifications still under discussion. The overall direction is to significantly upgrade all indicators, comprehensively enhancing training and inference performance. The preliminary consideration is that compared to the Ascend 960, the FP4 computing power, FP8 computing power, and interconnection bandwidth of the Ascend 970 will all double, with memory access bandwidth increasing by at least 1.5 times. The Ascend 970 is planned for release in Q4 2028. Everyone can look forward to its amazing performance.
This is the main specific specifications and roadmap of the Ascend chips I just introduced. Overall, we will continue to evolve at a pace of nearly doubling computing power every year, while focusing on ease of use, more data formats, and higher bandwidth to continuously meet the growing demand for AI computing power. It can be seen that compared to the Ascend 910B/910C, the main changes starting from the Ascend 950 include:
Introducing the new homogeneous SIMD/SIMT to enhance programming ease;
Supporting a richer variety of data formats, including FP32/HF32/FP16/BF16/FP8/MXFP8/HiF8/MXFP4/HiF4, etc.;
Supporting larger interconnection bandwidth, with the 950 series at 2TB/s and the 970 series increasing to 4TB/s;
Supporting greater computing power, with FP8 computing power increasing from 1 PFLOPS in the 950 series to 2 PFLOPS in the 960 and 4 PFLOPS in the 970; FP4 computing power increasing from 2 PFLOPS in the 950 to 4 PFLOPS in the 960 and 8 PFLOPS in the 970;
Memory capacity gradually doubling, while memory access bandwidth will quadruple.
With the Ascend chips as the foundation, we can create computing power solutions that meet customer needs. From the technical direction of building large-scale AI computing infrastructure, super nodes have become the dominant product form and are becoming the new norm in AI infrastructure construction. A super node is essentially a computer that can learn, think, and reason, physically composed of multiple machines but logically functioning as a single machine for learning, thinking, and reasoning. As the demand for computing power continues to grow, the scale of super nodes is also rapidly increasing.
In March of this year, Huawei officially launched the Atlas 900 super node, fully equipped to support 384 cards. As a super node, these 384 Ascend 910C chips can work like a single computer, achieving a maximum computing power of 300 PFLOPS. To date, the Atlas 900 remains the largest super node in the world. The CloudMatrix384 super node that you often hear about is a cloud service instance built by Huawei Cloud based on the Atlas 900 super node. Since its launch, over 300 sets of Atlas 900 have been deployed, serving more than 20 customers across various industries, including the internet, telecommunications, and manufacturing. It can be said that the Atlas 900 has opened the journey of Huawei’s AI super nodes in 2025.
Today, in conjunction with the Ascend chips we have launched or are developing, I will bring you more super node and cluster products. Now we enter the most exciting moment of today, which is the new product launch segment.
The first product I want to announce today is the Atlas 950 super node, built on the Ascend 950DT.
The Atlas 950 super node supports 8192 Ascend 950DT-based computing cards, which is more than 20 times that of the Atlas 900 super node. Each card corresponds to one Ascend 950DT chip, so 8192 computing cards are equivalent to 8192 Ascend 950DT chips.
The fully equipped Atlas 950 super node consists of 128 computing cabinets and 32 interconnection cabinets, totaling 160 cabinets, occupying an area of about 1000 square meters, with full optical interconnection between cabinets. The total computing power has significantly increased, with FP8 computing power reaching 8E FLOPS and FP4 computing power reaching 16E FLOPS. The interconnection bandwidth reaches 16PB/s, which means that the total interconnection bandwidth of the Atlas 950 product exceeds 10 times the peak bandwidth of the global internet today.
The Atlas 950 super node is scheduled to be launched in Q4 2026.
We are proud to see that the Atlas 950 super node will remain the world’s strongest super node in terms of computing power for at least the next few years, and it far exceeds major products in the industry in all key capabilities. For instance, compared to NVIDIA’s NVL144, which is also set to launch in the second half of next year, the Atlas 950 super node card’s scale is 56.8 times larger, total computing power is 6.7 times greater, memory capacity is 15 times larger, reaching 1152TB; interconnection bandwidth is 62 times greater, reaching 16.3PB/s. Even when compared to NVIDIA’s NVL576, which is planned for release in 2027, the Atlas 950 super node still leads in all aspects.
The significant enhancements in computing power, memory capacity, memory access speed, and interconnection bandwidth bring substantial improvements to large model training performance and inference throughput. Compared to Huawei’s already launched Atlas 900 super node, the training performance of the Atlas 950 super node has increased by 17 times, reaching 4.91M TPS. By supporting FP4 data format, the inference performance of the Atlas 950 super node has increased by 26.5 times, reaching 19.6M TPS.
The 8192 card super node is not our endpoint; we are continuing to strive for more. The second super node product I am announcing today is the Atlas 960 super node. Based on the Ascend 960, the Atlas 960 super node can support a maximum of 15488 cards. The Atlas 960 super node consists of 176 computing cabinets and 44 interconnection cabinets, totaling 220 cabinets, occupying an area of about 2200 square meters.
The Atlas 960 super node is scheduled to be launched in Q4 2027.
With the upgrade in card scale, the Atlas 960 super node further enhances our advantages in AI super nodes. Based on the Ascend 960, its total computing power, memory capacity, and interconnection bandwidth will double compared to the Atlas 950. Among them, the total FP8 computing power will reach 30E FLOPS, while the total FP4 computing power will reach 60 EFLOPS; memory capacity will reach 4460TB, and interconnection bandwidth will reach 34PB/s. The performance of large model training and inference compared to the Atlas 950 super node will increase by more than 3 times and 4 times, reaching 15.9M TPS and 80.5M TPS, respectively. Through the Atlas 950 and Atlas 960, we are confident in providing sustainable and abundant computing power for the long-term rapid development of artificial intelligence.
Super nodes have redefined the paradigm of AI infrastructure, but they are not limited to AI. In the field of general computing, we also believe that super node technology can bring significant value. From a demand perspective, core financial businesses still rely on mainframes and minicomputers, which have higher performance and reliability requirements compared to ordinary server clusters. General computing super nodes precisely meet these demands. From a technical perspective, super nodes can also inject new vitality into the general computing field.
Therefore, the Kunpeng processor will continue to evolve around supporting super nodes, with more cores and higher performance. At the beginning of Q1 2026, we will launch the Kunpeng 950 processor, which includes two versions: 96 cores/192 threads and 192 cores/384 threads; supporting general computing super nodes; with security features adding four layers of isolation, making it the first Kunpeng processor to achieve confidential computing in data center processors.
In Q1 2028, the Kunpeng processor will continue to break through key technologies in chip microarchitecture and advanced packaging technology, and will again launch two versions: a high-performance version with 96 cores/192 threads, with single-core performance improved by over 50%, mainly targeting AI hosts, databases, and other scenarios; and a high-density version with no less than 256 cores/512 threads, mainly targeting virtualization, containers, big data, and data warehousing scenarios.
Next is the third product I am announcing today: the TaiShan 950 super node, based on the Kunpeng 950, the world’s first general computing super node, which supports a maximum of 16 nodes, 32 processors, and a maximum memory of 48TB, while supporting memory, SSD, and DPU pooling.
This product is not just a technological upgrade in the general computing field; it significantly enhances business performance in general computing scenarios and helps financial systems solve core challenges. The current core challenge in replacing mainframes and minicomputers is the distributed transformation of databases, while the GaussDB multi-write architecture built on the TaiShan 950 super node does not require transformation but improves performance by 2.9 times, ultimately providing a smooth replacement for traditional databases on mainframes and minicomputers. The TaiShan 950 combined with distributed GaussDB will become the terminator of various mainframes and minicomputers, completely replacing traditional mainframes and minicomputers as well as Oracle’s Exadata database servers in various application scenarios.
In addition to core database scenarios, the TaiShan 950 super node also performs impressively in a wider range of scenarios: for example, improving memory utilization by 20% in virtualized environments, and reducing real-time data processing time by 30% in Spark big data scenarios.
The TaiShan 950 super node is scheduled to be launched in Q1 2026, so please stay tuned.
The value of super nodes is not only reflected in traditional intelligent computing and general computing business fields. The recommendation systems widely used in the internet industry are evolving from traditional recommendation algorithms to generative recommendation systems. We can build hybrid super nodes based on TaiShan 950 and Atlas 950 to open up a new architectural direction for the next generation of generative recommendation systems.
On one hand, through ultra-large bandwidth, ultra-low latency interconnection, and ultra-large memory, hybrid super nodes form an ultra-large shared memory pool, supporting PB-level recommendation system embedding tables, thus supporting ultra-high-dimensional user features; on the other hand, the ultra-large AI computing power of hybrid super nodes can support ultra-low latency inference and feature retrieval. Therefore, hybrid super nodes are a new choice for solutions aimed at the next generation of generative recommendation systems.
Large-scale super nodes push both intelligent computing and general computing capabilities to new heights, while also posing significant challenges to interconnection technology. As a leader in the connectivity field, Huawei is certainly not afraid of challenges. When defining and designing the technical specifications of the Atlas 950 and Atlas 960 super nodes, we encountered significant challenges in interconnection technology, mainly in two aspects:
The first is how to achieve long-distance and high reliability. Large-scale super nodes have many cabinets, and the interconnection distance between cabinets is long. Current electrical and optical interconnection technologies cannot meet the demand. Among them, current electrical interconnection technology has a short connection distance at high speeds, supporting at most two cabinets, while current optical interconnection technology can connect multiple cabinets over long distances but cannot meet reliability requirements.
The second is how to achieve high bandwidth and low latency. The current interconnection bandwidth between cards across cabinets is low, falling short of the super node’s demand by a factor of 5; the latency between cards across cabinets is large, with current interconnection technology achieving the best results of only around 3 microseconds, still leaving a 24% gap from the design requirements of Atlas 950/960. When the latency has already dropped to 2-3 microseconds, it is approaching the physical limit, and even a 0.1 microsecond improvement poses significant challenges.
Huawei, based on the technical capabilities built over thirty years, has systematically innovated to completely solve the existing problems in current technologies, exceeding the design requirements of the Atlas 950/960 super nodes, making ten-thousand-card super nodes possible.
First, to solve the problem of long-distance and high reliability, we introduced high-reliability mechanisms at every layer of the interconnection protocol, including the physical layer, data link layer, network layer, and transport layer; at the same time, we introduced nanosecond-level fault detection and protection switching in the optical path, allowing applications to remain unaffected when optical modules experience interruptions or failures; additionally, we redefined and designed optical devices, optical modules, and interconnection chips. These innovations and designs have improved the reliability of optical interconnections by 100 times, and the interconnection distance exceeds 200 meters, achieving the reliability of electricity and the distance of optics.
Secondly, to solve the problem of high bandwidth and low latency, we have broken through multi-port aggregation and high-density packaging technologies, as well as equal architecture and unified protocols, achieving TB-level ultra-large bandwidth and 2.1 microseconds of ultra-low latency. It is precisely because of a series of systematic and original technological innovations that we have conquered the interconnection technology for super nodes, meeting the requirements for high reliability, all-optical interconnection, high bandwidth, and low latency, making large-scale super nodes possible.
To meet the interconnection technical requirements of the Atlas 950/960 super nodes, and to ensure that a ten-thousand-card super node can still function as a single computer, Huawei has pioneered the super node architecture and created a new interconnection protocol that can support the architecture of ten-thousand-card super nodes. The core value proposition of the super node architecture based on this interconnection protocol is: a ten-thousand-card super node is a single computer, meaning that through this interconnection protocol, tens of thousands of computing cards can be connected into a super node that can work, learn, think, and reason like a single computer.
Technically, we believe that the architecture of a ten-thousand-card super node should have six major characteristics: bus-level interconnection, equal collaboration, full pooling, protocol unification, large-scale networking, and high availability. We have named this new interconnection protocol for super nodes “UnifiedBus” (UB).
Today, we officially announce the launch of UnifiedBus, an interconnection protocol for super nodes.
At the same time, I announce that Huawei will open the UnifiedBus 2.0 technical specifications. Why start opening from UnifiedBus 2.0? In fact, the research on UnifiedBus began in 2019. Due to well-known reasons, advanced processes were not available, and we needed to break through from multiple chips, hoping to connect more computing resources together. We named it UnifiedBus, which means achieving large-scale computing power connectivity, similar to the connectivity of nine provinces. The Atlas 900 super node, based on UnifiedBus 1.0, has been delivered since March 2025 and has been commercially deployed over 300 sets, fully validating the UnifiedBus 1.0 technology. Based on UnifiedBus 1.0, we continue to enrich functions, optimize performance, enhance scale, and further improve the protocol, forming UnifiedBus 2.0, with the previously announced Atlas 950 super node being based on UnifiedBus 2.0.
We believe that UnifiedBus 2.0 has met the conditions for openness. To promote the development of interconnection technology and industrial progress more broadly, Huawei has decided to open the UnifiedBus 2.0 technical specifications, welcoming industry partners to develop related products and components based on UnifiedBus and jointly build an open ecosystem for UnifiedBus.
As I emphasized at last year’s HC, based on the chip manufacturing processes available in China, we strive to create a “super node + cluster” computing solution to continuously meet computing power demands. Today, I have introduced three super node products. UnifiedBus is born for super nodes, serving as an interconnection protocol for super nodes and the optimal interconnection technology for building computing power cluster products.
Next, I will bring you two cluster products: first, the Atlas 950 SuperCluster with 500,000 cards!
The Atlas 950 SuperCluster is composed of 64 Atlas 950 super nodes interconnected, integrating over 520,000 Ascend 950DT chips from more than 10,000 cabinets into a single entity, with a total FP8 computing power of 524 EFLOPS. The launch time will be synchronized with the Atlas 950 super node, in Q4 2026.
In the cluster networking, we support both UBoE and RoCE protocols. UBoE carries the UB protocol over Ethernet, allowing customers to utilize existing Ethernet switches. Compared to traditional RoCE, UBoE networking has lower static latency and higher reliability, saving on the number of switches and optical modules, so we recommend UBoE.
This is our Atlas 950 SuperCluster. Compared to the current largest cluster in the world, xAI Colossus, its scale is 2.5 times larger, and its computing power is 1.3 times greater, making it the undisputed strongest computing cluster in the world! Whether for current mainstream training tasks of dense and sparse large models in the hundreds of billions or for future trillion and ten trillion large model training, super node clusters can serve as a powerful computing foundation, efficiently and stably supporting continuous innovation in artificial intelligence.
Correspondingly, in Q4 2027, we will also launch the Atlas 960 SuperCluster based on the Atlas 960 super node, further increasing the cluster scale to the million-card level, with total FP8 computing power reaching 2 ZFLOPS! FP4 total computing power will reach 4 ZFLOPS. It will also support both UBoE and RoCE protocols, and with the support of the UBoE protocol, performance and reliability will also be superior, with advantages in static latency and network fault tolerance further expanded, so we continue to recommend UBoE networking. Through the Atlas 960 SuperCluster, we will continue to accelerate customer application innovation and explore new heights of intelligence.
I am very pleased to present a series of new products today, and we hope to work with the industry to lead a new paradigm of AI infrastructure with the innovative UnifiedBus super node interconnection technology; to continuously meet the rapidly growing demand for computing power with super nodes and clusters based on UnifiedBus, promoting the continuous development of artificial intelligence and creating greater value. Thank you!
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