Intelligent evolution and the complexity of electronic and electrical architecture
As new energy vehicles enter the competitive second half, the empowerment of intelligence and the development towards the era of autonomous driving have become the main direction for the development of electric intelligent vehicles.
Driven by the gradual deepening of intelligence, a large number of components are being electrified, with smart cockpits and intelligent driving being widely applied. “Software-defined vehicles” have become a trend. Since the 1980s, the gradually introduced distributed electronic control units (ECUs) have increasingly struggled to meet the development needs of intelligent vehicles, leading to an urgent need for upgrades in automotive electronic and electrical (EE) architecture.
The evolution of automotive electronic and electrical architecture shows that while major manufacturers have detailed differences in their planning, the overall trend is evolving from distributed to domain control, then to domain integration and central control, ultimately moving towards a development trend that combines cloud control.
Figure 1: Development route of automotive EEA from distributed to centralized + informatization
From distributed to domain control and then to central control, ECUs are evolving towards SoC chips.
Looking at the evolution route of the EEA architecture, the current automotive electronic and electrical architecture is in the stage of evolving from domain control to domain integration, gradually exploring the development of central control.
Mainstream domestic and foreign automotive companies are developing towards domain control architecture. From the perspective of intelligent driving and controllers, the penetration rate reached 24% in April 2025, indicating that the industry is entering a growth phase.
From the technical situations of different companies, Tesla’s MODEL 3 uses a combination of central computer and regional controllers (left L, right R, front F), while other major domestic and foreign automotive companies are still developing based on functional domains and continuously promoting cross-domain integration.
Whether central control, regional control, or domain control, the integration and complexity of controllers have significantly increased. Traditional ECUs can no longer meet in-vehicle demands, and SoC chips have become an important foundation for the development of intelligent vehicles.
Figure 2: Schematic diagram of Tesla Model 3 electronic and electrical architecture
Figure 3: Zeekr automotive electronic and electrical architecture schematic
Figure 4: Characteristics of various electronic and electrical architectures
The dual domains of smart cockpit and intelligent driving drive the development of in-vehicle SoC.
Based on the commonly used functional domain distribution, after module centralization, smart connected vehicles are mainly divided into five domains: power domain, chassis domain, cockpit domain, autonomous driving domain, and body domain.
The power domain is mainly responsible for managing the powertrain, including the engine management system (EMS) and transmission control module (TCM) for traditional vehicles, as well as the vehicle control unit (VCU), motor control unit (MCU), and battery management system (BMS) for new energy vehicles.Due to low computing power requirements but high safety requirements, the main control chip is generally an ASIL-D level 32-bit MCU (microcontroller) chip.
The chassis domain is the core of vehicle dynamic control, covering four subsystems: steering, suspension, braking, and transmission, and accelerating the transformation towards deep collaboration in line control braking, steering, and active suspension. Due to being in a high safety scenario,the main control chip is still primarily ASIL-D level MCU.
The body domain is mainly responsible for integrating and managing the body electronic systems.Its core modules include lighting systems (low/high beam, turn signals, ambient lights), door/window and lock control systems (windows, sunroofs, electric tailgates), wiper and cleaning systems, heating and ventilation modules (seat/steering wheel heating), and body safety and anti-theft systems (PEPS, collision signal triggers). Due to the rich scenarios and the need for multiple interfaces, the basic requirement is ASIL-B level, with some reaching ASIL-D (when integrated with VCU) level, with the main control chip being MCU.
The cockpit domain and the newly added autonomous driving domain are the core battlegrounds for SoC chips.The cockpit domain focuses on centralized control of the cabin environment, including human-machine interaction, infotainment, and comfort, with high information processing density and some high safety requirements. The main control chip consists of SoC + MCU; the autonomous driving domain covers the core integration and control of vehicle perception, decision-making, and execution systems, with high computing requirements and high safety. The domain controller computing platform uses SoC chips + redundant safety MCU. In the current environment, cockpit and driving integration and central control are accelerating development, and SoC chips are also evolving in this direction.
Table 1: Technical analysis of the five domains of automotive under domain architecture
System-on-chip integration promotes the in-depth development of intelligent vehicles
SoC chips (System on Chip) are system-level chips that are highly integrated semiconductor products, integrating all components required for a complete electronic system into a single chip.
Typically, they include processor cores, memory, digital signal processors, communication modules, and power management units. This integrated design breaks through the limitations of traditional multi-chip discrete architectures, forming a complete system on a chip that can independently run operating systems and perform complex tasks.
Traditional MCUs are referred to as “microcontrollers”, which are integrated circuits that include a processor core (usually a microprocessor), memory (such as flash and RAM), and input/output (I/O) interfaces. Compared to MCUs, SoC chips integrate more heterogeneous processing units internally, have a more complex structural design, and possess stronger processing and computing capabilities. Their high performance, low power consumption, small size, and high reliability make them suitable for multitasking and more complex computational applications, such as advanced driver assistance systems, autonomous driving, and in-vehicle infotainment systems.
From a layman’s perspective, the design concept of SoC is “All in one”, a super platform for system integration, characterized by multi-core heterogeneous computing, large-capacity storage support, and complex functional modules;
whilethe design concept of MCU is “minimalism”, an expert in executing single tasks, characterized by a single-core CPU, only basic storage units, and necessary peripheral interfaces. Typically, MCUs are used to perform real-time tasks and directly control hardware; while SoCs run complete operating systems and handle complex algorithms such as image recognition, voice interaction, and autonomous driving.
Therefore, in smart cockpits and intelligent driving, SoCs and MCUs often coexist in a collaborative manner. For example, in autonomous driving, MCUs are responsible for executing real-time control and high-reliability tasks of the vehicle, such as engine control, steering control, and braking control, while managing in-vehicle communication; SoCs are used to support parallel computing and complex algorithms, processing multi-sensor perception data, and performing motion control. Due to the high complexity, additional mechanisms are often required to ensure safety. Therefore, safety-redundant MCUs are often present in intelligent driving domain controllers.
Figure 5: Horizon Journey 6 SoC chip “All in one” design concept
Table 2: Comparison of main features of MCU and SoC
Basic composition and performance indicators of SoC chips
From an internal structure perspective,MCUs integrate processors, memory, input/output interfaces, and other peripherals; SoC chips are system-level chips that, compared to MCUs, integrate more heterogeneous processing units, have a more complex structural design, and possess stronger processing and computing capabilities. From a hardware structure perspective, in-vehicle SoC chips typically also consist of processors, memory, and peripheral I/O, but are more complex than MCUs.
The processor is the brain of the SoC chip, which includes general logic operation units (CPU), AI acceleration units (NPU/BPU/TPU, etc.), image/video processing units (DSP/ISP, etc.), hardware security modules (HSM), and Safety MCU. Among them, the general logic operation unit is usually based on CPU implementation, responsible for managing software and hardware resources and executing system-level functional logic. The AI acceleration unit is used to handle large-scale parallel computing tasks and accelerate the execution of neural network algorithms. The image/video processing unit is based on DSP, ISP, GPU, etc., responsible for image signal calibration, 3D rendering, and video processing. The hardware security module (HSM) and Safety MCU are used for encryption services and real-time monitoring of the SoC’s internal state, ensuring system security.
Memory is generally divided into volatile and non-volatile types. Volatile memory such as SRAM and DRAM is used to store temporary data and currently executing programs; non-volatile memory such as NAND Flash and Nor Flash is used to store firmware programs and fixed data.
External I/O mainly consists of various interfaces: including general data interfaces (PCIe, LVDS, USB, SATA, CAN/CAN-FD, Ethernet, etc.), camera signal interfaces (MIPI-CSI-2, GMSL, FPD Link, etc.), audio interfaces (I2S, TDM, SPDIP, etc.), and display interfaces (DP, HDMI, etc.).
Table 3: Comparison of CPU, GPU, FPGA, and ASIC
Figure 6: Comparison of internal structures of MCU and SoC
Figure 7: SoC chip architecture
Basic composition and performance indicators of SoC chips
From a practical application perspective, the performance evaluation of SoC chips mainly includes: CPU computing power, GPU computing power, manufacturing process, storage bandwidth, AI computing power, energy efficiency, thermal management capability, connectivity and interface support, security, scalability, ecosystem, and support..
In terms of computing power: CPU computing power determines the smoothness of the system, affecting multitasking capabilities and application running efficiency. If the CPU computing power is insufficient, there may be a lag when switching applications in the cabin, usually evaluated using DMIPS to assess integer operation performance; in the cockpit,GPU computing power determines graphics processing capabilities, including support for multiple displays, resolution, and 3D graphics performance. In the autonomous driving layer, GPUs are also used to enhance deep learning and other autonomous driving algorithms, playing an important role in perception, decision planning, and testing optimization, evaluated using GFLOPS to assess floating-point operation performance;AI computing power is mainly used for intelligent functions in in-vehicle systems, such as automatic parking and voice recognition. Different SoC chips have different AI core solutions. For example, NVIDIA’s ORIN series provides AI computing power mainly through GPUs, while also featuring two dedicated modules: the ASIC-architecture Deep Learning Accelerator (DLA) and Programmable Vision Accelerator (PVA); Tesla’s FSD and Huawei’s Ascend chip NPU (Neural Processing Unit) are both ASIC architectures, while Horizon has developed its own ASIC-architecture BPU (Brain Processing Unit); Waymo uses a CPU + FPGA solution; generally, GPUs and FPGAs have better versatility, while ASICs are more specialized but also more efficient. In-vehicle computing platform SoCs generally adopt a heterogeneous design combining the above multiple computing units, often using MCUs for redundancy. AI processing capability is usually evaluated using TOPS (Tera Operations Per Second).
Storage bandwidth determines the speed of data transfer from memory to the processor, affecting application loading and data processing efficiency. The chip’s storage bandwidth is determined by the memory itself and the number of memory channels in the chip. 90% of the power consumption and latency in AI computing are due to data movement. Therefore, storage bandwidth also impacts the chip’s actual computing power.
Figure 8: NVIDIA ORIN CPU + GPU + DLA + PVA architecture and Horizon J6 four-core integrated solution
Table 3: Common SoC chip storage bandwidth information data
Basic composition and performance indicators of SoC chips
In addition to computing power requirements,SoC chips need to meet automotive-grade requirements in terms of process and safety, while also requiring high efficiency and low energy consumption. As computing power increases, the demand forthermal management also rises, as intelligent systems that operate at high intensity for long periods require good thermal management to avoid overheating that leads to performance degradation or system crashes. Additionally, the built-in security features of the chip (such as encryption, authentication, isolation, etc.) affect the system’s resistance to attacks, which is particularly important in intelligent driving and vehicle networking environments.
Interface, scalability, and ecosystem support: The chip’s support for various communication interfaces (such as CAN, Ethernet, USB, Wi-Fi, etc.) affects the system’s interaction with other devices; as functions and needs change, in-vehicle systems may need to add new sensors or functions. Chips with good scalability can reduce upgrade costs; at the same time, the development tools, software support, community, and documentation provided by chip manufacturers affect development efficiency and system stability.
Table 4: Comparison of basic requirements for chips in different application fields
Figure 9: Horizon J6’s rich high-speed interfaces
Figure 10: Horizon J6 hardware + toolchain + software ecosystem
As the core component of intelligent vehicles, SoC chips accelerate integration with downstream OEMs and direct connections with upstream suppliers.
The upstream of the SoC chip industry chain mainly includes IP core licensing, EDA (Electronic Design Automation) software and other design tool manufacturers, semiconductor materials, and equipment. Among them, IP core licensing and EDA software and other design tool manufacturers empower chip design companies, helping them accelerate the chip development cycle and time to market. Semiconductor materials and equipment manufacturers provide the basic materials and advanced equipment for chip manufacturing, ensuring high efficiency and high quality in chip production.
The midstream of the SoC chip industry includes three main links: chip design, chip manufacturing, and packaging/testing. Some companies have vertically integrated and are involved in all links, while others only participate in one link. Depending on the included links, these semiconductor companies’ business models are generally divided into vertical integration models (IDM model), wafer foundry models (Foundry model), and fabless models (Fabless model).
Tier 1 and automotive companies belong to the downstream of chip design companies. In the past industrial chain model, the entire supply chain was linear, with chip design companies as Tier 2, having close contact and cooperation with Tier 1, and little interaction with automotive companies. However, now many automotive companies actively seek communication and cooperation with leading chip companies to jointly research user needs and customize chips suitable for their own needs. This cooperation model not only enhances the competitiveness of automotive companies’ products but also helps ensure the stability of chip supply.
Figure 11: Structure of the SoC chip industry chain
Source: Guoyuan Securities Research Institute
