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2025.06
As global data center capital expenditures approach one trillion dollars, a restructuring of computing power driven by AI large models is rapidly disrupting traditional chip architectures.
Recently, the traditionally low-profile chip giant Marvell boldly declared at an investor summit: in the future, Marvell’s cloud revenue will fully transition to AI revenue. Custom computing (XPU) and XPU Attach (supporting components) are the two fastest-growing areas, with custom chips (ASICs) being key to meeting the demands of new workloads, representing the future of AI infrastructure, and happening “in every cloud”.
According to data cited by Marvell, global data center capital expenditures in 2023 are $260 billion, expected to exceed $1 trillion by 2028, with a compound annual growth rate of 20%. The market for “accelerated computing” chips specifically for AI is projected to reach $349 billion by 2028, including main control chips and peripheral supporting chips.
Among these, the market size for custom main chips is $146 billion, with an average annual growth of 47%; while the growth of custom supporting chips (such as memory managers, network interfaces, etc.) is even more astonishing, with a compound annual growth rate of 90%, and the market size is expected to reach $408 billion.
This data actually sends two clear signals: in the coming years, the global data center market will maintain rapid growth with high barriers to entry and strategic value for main chips; at the same time, the explosive growth of supporting chips presents a vast development space.
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The Strategic Turning Point of the Trillion Market – AI ASIC Opens the Golden Era
Marvell plays a “dark horse” role in the accelerated computing custom chip market, with a market share of less than 5% in 2023, but aims to achieve a 20% market share by 2028. Based on last year’s market expectation of $75 billion, Marvell has raised its target market size for custom chips in 2028 to $94 billion, with a compound annual growth rate of 35%. Among these, custom XPU is projected at $40 billion, with a compound annual growth rate of 47%; XPU supporting components are projected at $15 billion, with a compound annual growth rate as high as 90%.
Marvell’s full commitment to ASIC chips is a clear industrial signal, as evidenced by the AI ASIC layouts of giants like Meta and Broadcom.
Broadcom recently announced in its quarterly report that it expects the scale of AI ASIC deployment to continue to grow next year, with related revenues likely to far exceed the company’s previous expectations. Currently, Broadcom holds the top position in the ASIC market with a 55%-60% share. Broadcom’s core advantage in the AI chip field lies in customized ASIC chips and high-speed data exchange chips, whose solutions are widely used in data centers, cloud computing, high-performance computing, and 5G infrastructure.
Another noteworthy player is Meta. A report from Nomura Research indicates that Meta’s MTIA AI server could become a milestone in 2026. Meta plans to launch the AI ASIC (MTIA T-V1) in the fourth quarter of this year, with the MTIA T-V1.5 (V1.5) ASIC potentially launching in mid-2026, and the system achieving large-scale deployment in the second half of 2026. The performance of the MTIA T-V1.5 chip may be significantly more powerful than V1, with the intermediate layer size potentially twice that of V1, exceeding five times the mask size, similar to or slightly larger than NVIDIA’s next-generation GPU Rubin.
More and more cloud service providers are actively deploying their own AI ASIC solutions, and by 2026, TSMC’s AI logic semiconductor revenue is expected to see stronger growth for AI ASICs than for GPUs. Nomura believes that the total shipment of AI ASICs may surpass that of GPUs at some point in 2026.
Not only the main chips, but the competition for supporting chips in data centers is also highly intense. Recently, MediaTek successfully seized part of the design rights for Google’s data center TPU from Broadcom, thanks to its SerDes high-speed transmission technology and price advantage, marking a strong rise for MediaTek in the AI ASIC field. The core of MediaTek’s breakthrough lies in the SerDes high-speed transmission technology, which significantly enhances data transmission efficiency and anti-interference capability by serializing parallel signals, especially suitable for the I/O module design of TPU chips, and at a cost 15%-20% lower than Broadcom for equivalent performance, making it a key choice for diversifying Google’s supply chain.
It is worth noting that NVIDIA recently launched NVLink Fusion at Computex, which facilitates system-level integration with customized ASICs: through NVLink chipsets or IP integration, it achieves computational mixing with other dedicated TPUs, ASICs, or accelerators. This move itself is NVIDIA’s active embrace of the customization trend, rather than allowing customized chip projects to erode its market share. On the other hand, this also helps alleviate certain barriers in heterogeneous integrated computing for AI computing power infrastructure, objectively promoting the development and prosperity of ASIC chips.
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AI Control Chips – The “Heart Attack” of Domestic Computing Power
IDC data shows that by 2024, China’s accelerated chip market will exceed 2.7 million units. From a technical perspective, GPU cards occupy 70% of the market share; from a brand perspective, domestic AI chip shipments have exceeded 820,000 units, developing rapidly.
AI main chips are the core of computing power, determining the performance ceiling of AI clusters. Domestic AI chips have become a major target of U.S. technology sanctions against China, forcing domestic AI processors to continuously break through performance ceilings through architectural innovation, packaging integration, etc., further proving that density, efficiency, and scale are new levers for domestic computing power, such as:
Packaging Revolution: Huawei’s “Quad-Core Bridge + CoWoS-L” integration
Architecture Revolution: Qingwei Intelligent TX81 reconfigurable storage-computing integrated (RPU) architecture significantly improves computing power utilization
Cluster Revolution: Kunlun Core P800 XPU-P multi-core parallel architecture lights up a ten-thousand-card cluster
Huawei Super Node: From Single Card Disadvantage to System-Level Leap
Huawei Cloud’s CloudMatrix 384 super node marks a significant breakthrough in domestic AI computing power clusters. This system is built on 384 Ascend 910C chips, achieving a single cluster of 300 PFlops BF16 dense computing through a dual-chip packaging design (two chips share eight packaged memory and high-bandwidth interconnect), nearly double that of NVIDIA’s flagship GB200 NVL72 system, and achieving 2.1 times the memory bandwidth of the latter. In silicon flow tests, this cluster achieved a single NPU decoding throughput of 1943 tokens/s, with a computational efficiency of 1.29 tokens/s/TFLOPS, fully surpassing NVIDIA H100 and H800’s performance in the same scenario.
Ascend 910C is just the starting point; Huawei is further laying out the next generation leap through “quad-chiplet packaging”. This technology uses vertical interconnects in silicon interlayers, integrating four computing chips in a single package, with architecture comparable to NVIDIA’s 2026 Rubin Ultra platform. With packaging innovation and collaboration with local supply chains, Huawei’s next-generation chip costs are expected to be about 40% lower than NVIDIA H200, achieving performance parity through a strategy of “mature process clustering” and validating the technical breakthrough path of “exchanging packaging for process, enhancing efficiency through scale”.
Kunlun Core P800: Ten-Thousand-Card Cluster + MLA Engine Suitable for MoE Training
In 2020, Kunlun Core Generation 1 achieved mass production, mainly used for Baidu’s search engine and Xiaodu; the Kunlun Core Generation 2 produced in 2021 improved performance by 2-3 times compared to Generation 1; this year, the new generation Kunlun Core Generation 3 components have lit up a ten-thousand-card cluster.
Kunlun Core is based on an XPU dual computing unit architecture, with a hybrid computing engine consisting of a dedicated neural network processor XPU-SDNN (optimized for matrix multiplication/convolution and other tensor operations) and a general-purpose multi-core XPU cluster (handling complex control flows), sharing an instruction set to lower development barriers; tasks are dynamically allocated to the optimal engine by a unified scheduler, optimizing performance, efficiency, and flexibility.
The third-generation chip P800 is currently the most representative computing power product of Kunlun Core, with its XPU-P architecture adopting key technologies such as multi-core parallel computing, high-speed interconnect, and flexible programmability, which can well support large-scale training tasks of DeepSeek series MoE models, fully supporting features such as MLA (multi-head potential attention) and multi-expert parallelism, requiring only 32 units to support full parameter training of the model, efficiently completing continuous training and fine-tuning, and has currently lit up a ten-thousand-card cluster.
Cambricon Siyuan: Chiplet + LPDDR5 Innovation, Cloud Combat Power Leap
The Siyuan 370 chip is Cambricon’s first AI ASIC chip using chiplet technology, based on its intelligent chip architecture MLUarch03, with a maximum computing power of 256TOPS (INT8). The Siyuan 370 is also the first publicly released cloud AI chip in China to support LPDDR5 memory, with memory bandwidth three times that of the previous generation, and memory access efficiency reaching 1.5 times that of GDDR6. Equipped with MLU-Link multi-chip interconnect technology, it provides efficient collaboration for multiple Siyuan 370 chips in distributed training or inference tasks.
The latest generation of cloud intelligent training chip Siyuan 590 adopts MLUarch05 architecture, capable of providing larger memory capacity and bandwidth, with significant upgrades to I/O and inter-chip interconnect interfaces, greatly enhancing training performance.
Suizhi Cloud Suizhi Cluster: Deep Thought + High-Speed Interconnect, Reconstructing Storage-Computing Efficiency
Suizhi’s cloud Suizhi intelligent computing cluster can provide 1.2TB/s aggregated communication bandwidth within nodes (based on Suizhi Technology GCU-LARE interconnect technology), with three 200Gb/s (RDMA) transmissions between nodes, supporting high-speed communication in clusters, with a separated storage-computing network. The cluster is equipped with the AI chip Suizhi, which is also a representative work of Suizhi’s ASIC route.
The Suizhi chip architecture GCU-CARA (General Computing Unit and Global Computing Architecture) features fully programmable, all-mode computing, full-precision computing, and high parallelism, providing multi-data precision AI computing power support, offering leading performance for various computing paradigms such as tensors, vectors, and scalars, supporting instruction-driven, programmable fusion data flow architecture, providing software transparency and task-based intelligent scheduling.
Qingwei RPU Architecture: Violently Compressing Trillion Models to Run on a Single Machine
The Qingwei Intelligent TX81 is based on a reconfigurable storage-computing integrated (RPU) design, dynamically scheduling and allocating computing resources with higher efficiency when processing AI tasks through reconfigurable computing architecture mapping and data flow control technology, discarding traditional instruction processing flows and shared storage data exchange mechanisms, allowing hardware resources to focus more on core computing tasks.
Currently, Qingwei Intelligent computing power servers support self-organizing network scheduling without switches, significantly improving computing resource utilization and energy efficiency, supporting full model training from 1.5B, 7B to 600 billion parameters of the DeepSeek model, providing a cost-effective solution for supporting large models.
Supporting Chips – The Golden Track with 90% Growth Rate
The supporting chip market, with a compound annual growth rate of 90%, including memory interfaces, network interconnects, power management, etc., is the “golden track” for domestic enterprises. Although currently only the main chips are strictly considered AI chips, supporting chips are akin to the capillaries of ultra-large-scale AI clusters, working in synergy with main chips to ensure the overall efficiency and system security of AI systems.
High-Speed SerDes Billion-Dollar Blue Ocean, Domestic Manufacturers Compete for 112G
In the data center field, high-speed SerDes, as an important tool for data transmission, is expected to reach a market scale of billions of dollars in the future. High-speed SerDes IP is mainly applied in scenarios such as chip-to-chip interconnect (e.g., in PCIe/CXLPHY), Ethernet interconnect (e.g., in Ethernet switch PHY), and chip-to-optical module interconnect (e.g., in oDSP PHY). In data center scenarios, SerDes has high rate requirements, with international manufacturers generally researching above 112G, and even breaking through 224G.
The competitive landscape for domestic independent SerDes IP companies is still unstable, with startups continuously emerging, and most IP companies expanding their product lines for DDR, USB, MIPI, and other interfaces. Independent manufacturers laying out high-speed SerDes-related IP include Shenglian Technology, Xinchao Flow, Jiyiwe, Xinyuan, Hejian Gongruan, and Xinyaohui.
Shenglian Technology is a high-speed interface IP supplier, offering high-speed SerDes and UCIe IP, PCIe6.0 high-speed interface IP solutions. Among them, the 112G SerDes IP solution is based on ADC/DSP receiving architecture, supporting PAM4 and NRZ transmission, and long-distance transmission: 42dB@112G PAM4.
Xinchao Flow is a joint venture of Alphawave in China, supporting the sales and customization of Alphawave high-speed SerDes IP in China. Xinchao Flow adopts SerDes technology based on DSP algorithm architecture, effectively meeting the real-time transmission needs of high-bandwidth data, which is also the mainstream direction in the current market.
Hejian Gongruan has launched 56G/112G Serdes Controller IP, and recently released the UniVista 32G Multi-Protocol SerDes IP, consisting of hardened modules (PMA/SerDes) and RTL modules (Raw PCS), supporting a data transmission rate of 32 Gbps (e.g., 32.0GT/s at PCIe Gen5 rate), supporting various mainstream and dedicated protocols such as PCIe Gen1-5, USB4, Ethernet (25GKR, 10GKR), SRIO, JESD204C.
Jiyiwe has already achieved mass production of 56G Serdes IP in China, and 112G Serdes IP has also been taped out. Its main business includes the R&D and industrialization services of high-performance and low-power PLL, ADC/DAC, as well as SerDes IP and IC.
Xinyaohui has a relatively complete interface IP product line, providing IP solutions for different foundries at various process nodes of 1-10G/20G/25G/32G/56G/112G multi-protocol SerDes PHY, which can support various protocols including PCIe, USB, DP, MIPI, MPHY, Ethernet.
Xindong Technology has 32G/56G/64G SerDes solutions, including PCIe6/5 (backward compatible with PCIe4/3/2), USB3.2/3.0, SATA, XAUI, SATA, RapidIO, CXL2.0, and the latest 112G SerDes is also under development, with flexible customization of Retimer and Switch chips.
From Power to Storage, the “Security Defense Battle” of Domestic Chips
Power management, computing, and storage acceleration chips are also important supporting chips for data center infrastructure, among which power management can be further subdivided into core processor power supply, memory power supply, and circuit protection.
Power Management and Protection
Xidi Micro focuses on power supply chips for core processors such as CPU, GPU, DSP, with innovative architecture and good load transient response, output current of 50A, efficiency exceeding 90%, and multiple parallel connections can output higher specifications of current, meeting the demand for miniaturization and efficiency of power modules in AI servers compared to mature solutions from international brands. In addition, Xidi Micro’s series products such as 20A/50A high-current E-fuses load switch chips also perform well in key indicators such as current limit accuracy and response time.
Huiyixin specializes in power management chips for core processors such as CPU/GPU, with its DrMOS products entering the supply chain of several leading companies and achieving mass shipments. Currently, the motherboard power supply system solution is a multi-phase power supply, i.e., a combination of multi-phase controller chips + DrMOS chips. Among them, the DrMOS chip (Driver MOS) is the power management chip that performs the specific actions of voltage reduction control (belonging to DC-DC), integrated from a driver IC and MOSFET (main switch + freewheeling diode).
Jiewate responds to the trend of upgrading PMIC multi-phase controllers to higher phase counts in high current scenarios, launching the 12-phase controller JWH6377, which features programmable loop configuration; 6*6 QFN packaging; and flexible adjustment of dual-path phase sequence configuration, etc. In addition, it integrates PMBus voltage regulation functions, capable of reporting key voltage, current, power, temperature, and fault information; integrates current balancing and thermal balancing functions for each phase, optimizing current distribution and thermal stress; and integrates various protection functions, providing different fault response types.
SiYuan Semiconductor has entered the storage power supply field from DDR5 PMIC. The SY5888 and SY5887 PMICs are designed specifically for DDR5 memory modules, integrating three high-efficiency buck converters and precise voltage regulation modules, with SY5888 supporting memory overclocking to over 8000Mbps. Compared to traditional DDR4, DDR5 power supply needs to cope with high-frequency fluctuations and stringent voltage precision requirements, and SiYuan’s dynamic voltage regulation technology allows the chip to maintain “calm output” under high load. In addition, enterprise-grade DDR5 memory modules are temperature-sensitive, and SiYuan’s TS5110 sensor has an accuracy of ±0.25°C, with its stress compensation algorithm improving mass production consistency.
2. Storage Control
Yixin Technology PCIe4.0 SSD controller chip STAR2000 has been taped out. This chip integrates a neural network processing unit, combining 8TOPS of AI computing power to customize near-storage computing or in-storage computing functions for data center services, also helping SSDs improve reliability and service quality, optimize power consumption, and achieve intelligent self-checking and early fault diagnosis. It adopts a 12nm process and supports NVMe2.0 protocol, providing good steady-state random and sequential read/write performance.
Lanqi Technology in memory interface chips, its DDR5 RCD (Register Clock Driver) and DB (Data Buffer) set are core components of high-performance server memory modules (RDIMM/LRDIMM), capable of enhancing CPU access speed and stability to memory. In addition, there are DDR5 memory module supporting chips, including SPD Hub, PMIC, and temperature sensors, achieving fine management of memory power supply and temperature control; clock driver (CKD) chips are breakthrough applications in high-end memory modules for clients (such as CUDIMM/CAMM), meeting the next generation computing platform’s demand for higher memory bandwidth.
In Conclusion
As AI extends from training to inference scenarios, ASIC chips have also become the preferred choice for enterprises due to their energy efficiency advantages. Industry data shows that by 2025, the global ASIC market is expected to reach $22 billion, with AI-related share accounting for 15%, and is expected to exceed $40 billion by 2030. As AI computing power infrastructure moves towards heterogeneous integration, domestic ASIC chip manufacturers are facing unprecedented opportunities.
Through years of development, domestic chip manufacturers have formed a certain accumulation in underlying technologies, as mentioned earlier, such as significant breakthroughs in key supporting chip fields like high-speed SerDes interconnects, high-efficiency power supply (such as high-current DC/DC, multi-phase controllers, DrMOS), advanced storage control (such as PCIe 4.0/5.0 SSD controllers, DDR5 interfaces and management), as well as signal chains and interfaces, forming systematic capabilities. These are the core cornerstones for building high-performance, highly integrated, low-power ASICs, providing solid guarantees for further upgrades of domestic manufacturers on the ASIC path.
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