Democratizing 3D Integration: A Low-Cost Prototyping Solution Based on Chip-Level Thinning, Through-Silicon Vias (TSV), and Meta Bonding

Original link: https://xplorestaging.ieee.org/document/11007580【Abstract】 Three-dimensional integrated circuit (3D-IC) technology, with its vertical interconnections through silicon vias (TSV), has become central to advanced semiconductor devices. However, the initial development costs are prohibitively high, primarily due to the substantial investment required for wafer-level TSV processes. This study proposes…