Today, while studying the asynchronous FIFO read and write clock synchronization in FPGA, I noticed an issue: when connecting two different clocks, it is challenging to achieve complete synchronization. As a result, at a certain moment, the edge of the high-precision clock may appear in the middle of the edge of the low-precision clock, leading … Read more
This series of articles will delve into the CDC issues, introducing CDC handling, CTS, and CDC timing constraints. If you’re interested, feel free to follow.The previous article 【Series】Detailed Explanation of Digital IC/FPGA Cross-Clock Domain Issues (4) Deep Understanding of Metastability (Part 2) introduced the probability of metastability and the estimation method for MTBF. This section … Read more
In FPGA design, handling cross-time domain (Cross-Time Domain, commonly referred to as Cross Clock Domain CDC) is a key technology to ensure reliable signal transmission between different clock domains, with the core issue being the resolution of the metastability problem. 1. Single Bit Signal Crossing Domain: Two-Stage Synchronizer This is the most basic method, suitable … Read more
This series of articles will delve into the CDC issues, introducing CDC handling, CTS, and CDC timing constraints. Interested readers are encouraged to follow.The previous article in this series, 【Series】Detailed Explanation of Digital IC/FPGA Cross-Clock Domain Issues (1) Synchronous and Asynchronous Clocks, introduced synchronous/asynchronous clocks and the limitations of fully synchronous designs. This article will … Read more
The CDC (Cross-Clock Domain) issue is a core topic in FPGA/Digital IC interviews. Since most students’ FPGA/Digital IC projects primarily involve synchronous clock processing, many people still have a theoretical understanding of CDC issues, and they struggle to respond when the question type changes.This series of articles will delve into CDC issues, introducing CDC handling, … Read more