Composition and Measurement of Computing Power: Architectures of CPU, GPU, NPU, and More

Composition and Measurement of Computing Power: Architectures of CPU, GPU, NPU, and More

Composition and Measurement of Computing Power: Architectures of CPU, GPU, NPU, and More Composition: The core of computing power (computational capability) is the number of calculations a processor can complete in a unit of time. This is based on the processor’s clock frequency, core count, parallel processing capability, and memory bandwidth. Measurement: FLOPS is the … Read more

8-Channel Transceiver Core Board

8-Channel Transceiver Core Board

Overview APCore8T8R is an 8-channel transceiver core board, with an FPGA chip using the Xilinx ZYNQ UltraScale+ RFSoC ZU47DR, dimensions 105x84mm (the size of two standard IC cards). Introduction The onboard resources are as follows: 4GB PS DDR4; 2GB PL DDR4; 64GB EMMC; 128MB FLASH; Ethernet physical layer; onboard RF SMA x8; mini-SMP x8; users … Read more

Beyond Stability: Designing Load Point Power Supplies with Ultra-Fast Transient Response for FPGAs and SoCs

Beyond Stability: Designing Load Point Power Supplies with Ultra-Fast Transient Response for FPGAs and SoCs

Click to enter the Kuaiyi procurement mini-program ➡️, a bearing industrial control electronics procurement platform with 500,000 registered users and over 5,000 real-time demands updated daily. Why not take a look? Abstract At the pinnacle of modern digital computing, FPGAs (Field Programmable Gate Arrays) and SoCs (System on Chip) are like performance beasts, processing data … Read more

Exploring the xclbin File Format of FPGA (Part 2)

Exploring the xclbin File Format of FPGA (Part 2)

Click the blue text to follow us Exploring the xclbin File Format of FPGA (Part 2) [[0x1 Introduction]] [[0x2 Advanced Features of xclbin Files]] [[0x3 Security Mechanisms of xclbin Files]] [[0x4 Loading and Verification of xclbin Files]] [[0x5 Toolchain Analysis of xclbin Files]] [[0x6 Conclusion]] 0x1 Introduction In the previous article, we delved into the … Read more

Handling Cross-Time Domain in FPGA Designs

Handling Cross-Time Domain in FPGA Designs

In FPGA design, handling cross-time domain (Cross-Time Domain, commonly referred to as Cross Clock Domain CDC) is a key technology to ensure reliable signal transmission between different clock domains, with the core issue being the resolution of the metastability problem. 1. Single Bit Signal Crossing Domain: Two-Stage Synchronizer This is the most basic method, suitable … Read more

FPGA Tutorial Case 12: Design and Implementation of a Complex Multiplier Based on Vivado IP Core

FPGA Tutorial Case 12: Design and Implementation of a Complex Multiplier Based on Vivado IP Core

01Design and Implementation of a Complex Multiplier Based on Vivado IP CoreIn the fields ofdigital signal processing and image processing, complex multiplication is often required. A complex multiplier is a core component for performing this operation. Particularly in digital signal processing, complex multiplication has numerous applications, including signal mixing, FFT, and IFFT. The complex multiplier … Read more

Electronic Paper Displays Enter the LCD Screen Domain

Electronic Paper Displays Enter the LCD Screen Domain

Click the blue text to follow us SUBSCRIBE to US Source image: Modos Electronic paper displays are highly regarded for their readability and low power consumption, but have long been considered too slow for everyday computing use. Modos, a two-person startup rooted in open hardware, believes it has solved part of the problem — launching … Read more

Good News | Zhengling Holdings’ Invested Company ZKXMC Successfully Achieves Mass Production of MC1P170-FC676L

Good News | Zhengling Holdings' Invested Company ZKXMC Successfully Achieves Mass Production of MC1P170-FC676L

Recently, Zhengling Holdings’ invested company — ZKXMC has successfully achieved mass production of the self-developed “Mgicubo” series FPGA product MC1P170-FC676L on the first attempt! This product is positioned for mid-to-high-end performance, targeting complex application scenarios and high-speed interconnect requirements, demonstrating excellent technical stability and industrial maturity. In the context of increasing competition in the global … Read more

Libero® SoC Design Suite Achieves Dual Safety Certification!

Libero® SoC Design Suite Achieves Dual Safety Certification!

Friends in the chip industry, I have exciting news that will make your heart race! Libero® SoC Design Suite 2023.2 SP1 has officially passed the TÜV® Rhineland’s ISO 26262 ASIL-D and IEC 61508 SIL-3 dual certifications, compatible with SmartFusion® 2, IGLOO® 2, and PolarFire® FPGA and SoC devices. These two “safety gold medals” are not … Read more