Composition and Measurement of Computing Power: Architectures of CPU, GPU, NPU, and More
Composition: The core of computing power (computational capability) is the number of calculations a processor can complete in a unit of time. This is based on the processor’s clock frequency, core count, parallel processing capability, and memory bandwidth.
Measurement: FLOPS is the most commonly used metric for measuring computing power, representing the number of floating-point operations executed per second. Common units include TFLOPS (trillions) and PFLOPS (quadrillions). It is often used in high-performance computing scenarios such as scientific calculations and AI training. TOPS indicates the number of trillion operations that can be executed per second, commonly used to measure the integer operation performance of AI accelerators (like NPU), especially in inference tasks.
Architectures:
CPU: Central Processing Unit. It adopts the von Neumann architecture, emphasizing control and generality. It has a powerful ALU and a complex Control Unit (CU), excelling at handling complex serial tasks and logical branches. It is the “brain” and command center of the computer system.
GPU: Graphics Processing Unit. It employs a massively parallel processing architecture with thousands of streamlined computing cores. Originally designed for graphics rendering, it has now become the preferred choice for data-parallel computing (such as AI training, deep learning, and scientific simulations), excelling at performing the same simple operations on large datasets.
NPU: Neural Processing Unit. It is a type of application-specific integrated circuit (ASIC) optimized at the hardware level for neural networks (such as convolution, matrix multiplication, and addition). It adopts architectures like near-memory computing and 3DCube, pursuing extremely high energy efficiency, specifically designed to accelerate the inference and training processes of AI models, commonly found in mobile SoCs and cloud AI chips. For example, the Ascend AI chip is Huawei’s self-developed neural network processing chip (NPU).
FPGA (Field-Programmable Gate Array)
FPGA is a semi-custom chip whose hardware logic can be programmed and reconfigured according to user needs using hardware description languages. It combines the high performance of hardware with the flexibility of software, commonly used for algorithm prototyping, specific task acceleration (such as network processing, signal processing), and scenarios with strict requirements for latency and power consumption.
ASIC (Application-Specific Integrated Circuit)TPU
ASIC is a chip tailored for specific applications or algorithms and cannot be reconfigured like an FPGA. Its design goal is to achieve extreme performance and energy efficiency for a particular task. Google’s TPU (Tensor Processing Unit) is a typical representative of ASIC, specifically designed for matrix multiplication and addition operations in neural networks, playing a core role in Google’s cloud AI training and inference. NPU can essentially be viewed as a type of ASIC focused on neural network processing.
DPU (Data Processing Unit)
DPU is a new generation of dedicated processors, primarily designed to efficiently handle infrastructure tasks in data centers, such as network protocol parsing, data encryption and decryption, and storage virtualization. It can free the CPU from heavy system-level tasks, allowing it to focus more on running applications, thereby improving the overall computational efficiency of the data center. DPU is key to achieving “East-West” data processing and cloud-native architectures.
Brain-like Computing Chips (Neuromorphic Chips)
This is a new architecture inspired by the structure and operation mechanisms of human brain neurons, represented by Intel’s Loihi chip. It uses asynchronous circuits to simulate spiking neural networks (SNN), characterized by event-driven, highly parallel, and extremely low power consumption, making it very suitable for real-time pattern recognition and continuous learning at the edge, representing a cutting-edge exploration direction.
In summary, modern computing architectures have entered the era of heterogeneous computing. The CPU serves as the general control center, the GPU acts as the main force for large-scale parallel computing, NPU/ASIC (TPU) undertakes dedicated AI computing, FPGA provides flexible acceleration, and DPU handles data scheduling, collectively forming a collaborative “computing power engine” to meet the diverse needs of various artificial intelligence application scenarios.