eFPGA

In-Depth Analysis of the 2025 FPGA Competition Topic 2: How FPGA Solves the Challenges of Real-Time Performance and Accuracy in Industrial Inspection

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In-Depth Analysis of the 2025 FPGA Competition Topic 2: How FPGA Solves the Challenges of Real-Time Performance and Accuracy in Industrial Inspection

Click the blue text Follow us Pengye Jiatu Technology September 19, 2025 Issue 4: In-Depth Analysis of the 2025 FPGA Competition Topic 2 Analysis Hello everyone, we are Pengye Jiatu Technology~ In this issue, we will bring you an analysis of the 2025 FPGA Innovation Design Competition Topic 2, with over 7000 words of detailed … Read more

Overview of Xilinx 7 Series FPGA Chips

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Overview of Xilinx 7 Series FPGA Chips

Click the blue text to follow us Follow and star our public account for exciting content delivered daily. Source: Online materials The Xilinx 7 series chips are widely used, characterized by low cost, strong performance, and mature stability. Currently, Xilinx (AMD) has extended the lifecycle of this series of chips at least until 2035. This … Read more

Detailed Explanation of Asynchronous Reset and Synchronous Release in Digital IC/FPGA Cross-Clock Domain Issues (5)

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Detailed Explanation of Asynchronous Reset and Synchronous Release in Digital IC/FPGA Cross-Clock Domain Issues (5)

This series of articles will delve into the CDC issues, introducing CDC handling, CTS, and CDC timing constraints. If you’re interested, feel free to follow.The previous article 【Series】Detailed Explanation of Digital IC/FPGA Cross-Clock Domain Issues (4) Deep Understanding of Metastability (Part 2) introduced the probability of metastability and the estimation method for MTBF. This section … Read more

I2C Driver for FPGA Function Module

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I2C Driver for FPGA Function Module

1. Introduction to I2C Reference Source https://blog.csdn.net/Teminator_/article/details/141224886 1.1 Overview of I2C Bus (1) The IIC protocol (Inter-Integrated Circuit, abbreviated as I2C) is a serial communication protocol used for communication and data exchange between various electronic devices. It was first proposed and promoted by Philips in 1982 as a simple, efficient, and low-cost communication protocol. (2) … Read more

FPGA Multirate Signal Processing

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FPGA Multirate Signal Processing

In fields such as wireless communication, digital audio, and radar systems, we often face a dilemma: we want to ensure accuracy with high sampling rates during signal acquisition, but we also need low rates during processing to reduce costs. Multirate Signal Processing is the “variable speed engine” that resolves this dilemma. It achieves a balance … Read more

Introduction to FPGA: Implementing Shift Registers with Verilog/VHDL

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Introduction to FPGA: Implementing Shift Registers with Verilog/VHDL

What is a shift register? In FPGA (or ASIC), a shift register is a very common basic module. Its essence is to connect multiple flip-flops (registers) in a chain. All flip-flops share the same clock signal, and the output of each flip-flop is connected to the input of the next flip-flop. In this way, data … Read more

Why ‘Hardware-Software Co-design’ is a Must for FPGA Engineers? A Comprehensive Guide to the National RK+FPGA Development Board for the Ziguang Tongchuang Cup Challenge 3

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Why 'Hardware-Software Co-design' is a Must for FPGA Engineers? A Comprehensive Guide to the National RK+FPGA Development Board for the Ziguang Tongchuang Cup Challenge 3

The requirements for Challenge 3 and the eight-channel video input solution can be found at the link below.[Challenge Release] The 2025 National College Student FPGA Innovation Design Competition Ziguang Tongchuang Cup invites you to spread your wings and embark on a journey in chip technology![Challenge Tutorial] A reference solution for implementing eight-channel video input based … Read more

Near-Sensor, Low-Latency, Data Fusion Sensor Hub in AI Systems

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Near-Sensor, Low-Latency, Data Fusion Sensor Hub in AI Systems

Abstract Lattice Semiconductor has launched a sensor hub based on FPGA technology, providing support for the development of intelligent robots. It features flexible I/O interfaces and supports parallel computing near the sensors, enabling connections with multiple sensors and actuators while achieving low-latency and low-power computation. This sensor hub can undertake low-level real-time computing tasks specific … Read more

FPGA Hardware Development – DDR Design

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FPGA Hardware Development - DDR Design

1. Hardware Circuit Design (Basic Assurance) Power Supply and Ripple Control The core power supply (e.g., 1.2V for DDR4) should be independently powered, paired with a capacitor array of 10μF + 0.1μF, with ripple control within ±5%; Termination resistors (ODT) should be placed close to the DDR chips, with matched impedance (typically 50Ω/60Ω) to reduce … Read more