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Abstract
At the pinnacle of modern digital computing, FPGAs (Field Programmable Gate Arrays) and SoCs (System on Chip) are like performance beasts, processing data at astonishing speeds while consuming power in unprecedented ways. The traditional power supply design philosophy—pursuing voltage stability under steady-state conditions—falls short in the face of such loads. This article will delve into a more stringent and decisive performance dimension: ultra-fast transient response. We will start from the quantifiable “target impedance” theory, analyzing the control architecture that achieves nanosecond-level response, the art of designing multi-stage capacitor networks, and the “devilish details” in physical layout, revealing how to design a truly robust and responsive load point (PoL) power supply for these digital “hearts”.
Chapter 1,
WEEKLY REPORT
Redefining Challenges—From “Voltage Ripple” to “Target Impedance”
For a long time, the main metric for evaluating the performance of a PoL power supply has been its output voltage ripple under steady-state conditions. However, for an FPGA core executing intensive algorithms, its operating state is not “steady-state”. Its current consumption can surge from a few amperes (A) at near-idle to dozens or even hundreds of amperes at full load within just a few tens of nanoseconds. This load transient is the most severe test for PoL power supplies.
When the load current experiences a sharp change (di/dt), the inevitable inductance and resistance in the power distribution network (PDN) will cause an instantaneous voltage droop at the FPGA’s power pins. If this droop exceeds the chip’s allowable operating voltage range, it can lead to computation errors, performance degradation, or even system resets or crashes.
To transform this issue from a vague qualitative description into a computable, designable engineering target, we must introduce a core concept—target impedance (Target Impedance, Z_target).
The calculation formula is very simple, yet it contains profound design philosophy:
Z_target (Ω) =
V_droop_max (V) / ΔI_transient_max (A)
Where:
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V_droop_max
is the maximum voltage droop allowed during transient response as specified in the chip’s datasheet. For example, a 1.0V core power supply may allow a ±3% fluctuation, i.e., V_droop_max = 30mV.
-
ΔI_transient_max
is the maximum current step that the chip may experience. For instance, a transition from a standby current of 2A to a peak current of 50A results in ΔI_transient_max = 48A.
Based on the above data, we can calculate the target impedance for this PoL power supply’s PDN:
Z_target =
30mV / 48A ≈ 0.625 mΩ (milliohm)
This 0.625mΩ is the “gold standard” for our entire power supply system design. It means that from the output of the PoL voltage regulator (VRM), through PCB traces and vias, to the FPGA’s power balls (BGA Ball), the total impedance must remain below this value across the entire frequency range of interest (from DC to hundreds of MHz or even GHz).
This diagram clearly reveals the daunting nature of the challenge: our task is to suppress this blue impedance curve below the red line across all frequency bands through the collaborative efforts of the VRM, bulk capacitors, ceramic capacitors, and chip packaging/on-chip capacitors.
Chapter 2,
WEEKLY REPORT
The Revolution of Control Architecture—How COT Achieves “Proactive” Control
To achieve ultra-fast transient response, the “brain” of the PoL power supply—the control IC’s control architecture—plays a decisive role. Traditional control modes are inadequate under such extreme challenges.
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Voltage Mode Control: This is the most classic control method, but it has a double pole in its loop, requiring a complex Type III compensation network, which typically limits its loop bandwidth to 1/10 to 1/5 of the switching frequency, resulting in the slowest response.
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Current Mode Control: By introducing an internal inductor current loop, it simplifies compensation (only requiring Type II), improving response speed. However, it still follows a “post-compensation” logic, adjusting the duty cycle gradually after detecting a voltage droop.
In the face of nanosecond-level load steps, we need a “proactive” control strategy. This is where the COT (Constant On-Time) control architecture and its advanced variants (such as TI’s D-CAP™/D-CAP2™/D-CAP3™, Infineon’s Multi-layer Control, etc.) shine.
The core idea of COT control:
The COT architecture does not rely on a traditional, bandwidth-limited error amplifier and oscillator. Its comparator directly monitors the output voltage. Once the output voltage drops below the reference voltage threshold due to a load surge, the comparator will immediately trigger the upper bridge MOSFET to turn on for a fixed time (On-Time) without waiting for the next clock cycle.
The advantages of this mechanism are revolutionary:
- Near-instantaneous response: It eliminates delays from error amplifier integration, compensation network delays, etc., resulting in extremely low response latency, which can be considered “zero-latency” response.
- Extremely high loop bandwidth: Its equivalent loop bandwidth can be made very high, easily handling MHz-level load changes.
- Adaptive frequency: During load transients, its switching frequency will automatically increase to pump energy to the output capacitor as quickly as possible, thereby minimizing voltage droop.
Of course, early COT control relied on the ESR of the output capacitor to generate ripple as the comparator’s trigger signal, which limited the application of all-ceramic capacitor solutions. However, modern enhanced COT architectures (such as D-CAP2™/D-CAP3™) perfectly solve this problem by generating ripple compensation signals internally while retaining their lightning-fast response speed.
Design Conclusion: For powering FPGAs/SoCs that demand extreme transient response, using advanced COT control architecture PoL controllers or modules is a prerequisite for success.
Chapter 3,
WEEKLY REPORT
The Art of Multi-Stage Capacitor Networks—Building a Wideband Low-Impedance “Reservoir”
The COT controller provides the ability to “open the faucet at the fastest speed”, but if the pipes are thin and the reservoir is small, it still cannot meet the instantaneous high water demand. This “reservoir” is our output capacitor network. Constructing a capacitor network that maintains extremely low impedance across a wide frequency band is an art of balancing cost, space, and performance.
Our goal is to “flatten” the PDN impedance curve, which requires the collaborative efforts of different “engineers”:
First Line of Defense: Bulk “Reservoir”—Polymer/Tantalum Capacitors
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Role: To handle lower frequency (DC ~ 500kHz) and longer-duration load transients, they serve as the primary energy storage units.
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Key Selection Criteria: **Extremely low ESR (Equivalent Series Resistance)** is more important than capacitance value itself. A polymer capacitor with an ESR of 5mΩ and 470µF outperforms a standard aluminum electrolytic capacitor with an ESR of 50mΩ and 1000µF. Low ESR ensures minimal voltage drop during high current discharge.
Second Line of Defense: Midfield “Main Force”—Multi-Layer Ceramic Capacitors (MLCC)
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Role: To address mid-to-high frequency (500kHz ~ 100MHz) transient demands. They are the main force in reducing PDN impedance and determining the “depth” and “recovery speed” of transient response.
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Design Art—”Distributed, Multi-Model”:
1. Distributed Placement: Place MLCCs as widely as possible and close to the FPGA’s power pins. Because at high frequencies, the inductance of PCB traces dominates, and distance is everything.
2. Multi-Model Parallelization: This is the essence of design. Simply stacking the same large-capacity MLCC (e.g., 100 pieces of 22µF) is incorrect. Each capacitor has its self-resonant frequency (SRF), and above the SRF, it becomes inductive. The correct approach is to use a combination of multiple different capacitance values of MLCCs (e.g., 20 pieces of 47µF + 40 pieces of 10µF + 60 pieces of 1µF + 100 pieces of 0.1µF), utilizing their different self-resonant points to provide a low-impedance path across a very wide frequency range.
3. Beware of Invisible Killers: Pay attention to the DC Bias Effect of MLCCs, as the actual capacitance of Class II ceramic capacitors significantly decreases with increasing applied DC voltage. Additionally, prioritize packages with low ESL (e.g., 0402 is better than 0603, and reverse geometry packages are even better).
Third Line of Defense: Chip’s “Close Bodyguard”—Packaging/On-Chip Capacitors
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Role: To address the highest frequency (> 100MHz) transient demands, this is the work of chip designers and packaging engineers. As system designers, what we can do is trust their designs and provide them with as quiet an external power environment as possible.
Chapter 4,
WEEKLY REPORT
Physical Realization—When Layout Determines Everything
A theoretically perfect schematic, if implemented with a poor PCB layout, can see its transient performance drop by an order of magnitude. In high-speed PoL design, layout and routing are not merely finishing touches, but core components of the design.
The Golden Rule:
- Shortest Path Principle: PoL voltage regulators must be physically close to the FPGA/SoC. The area of the high-frequency current loop formed from the output of the VRM, through the output capacitors, to the FPGA power pins must be minimized to reduce parasitic inductance.
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The “Onion Model” of Capacitor Placement:
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Place large-capacity polymer capacitors near the VRM output.
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Place medium-capacity MLCCs (e.g., 10µF/47µF) around the FPGA.
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Place the smallest capacity, lowest ESL MLCCs (e.g., 0.1µF/1µF) on the back of the FPGA, directly facing the power pins, connected through the shortest vias.
The Art of Power/Ground Planes:
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Use complete, uninterrupted power and ground planes to power the FPGA. Planes provide the lowest inductance path.
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Inner planes are better than outer planes because they can form tighter electromagnetic field coupling.
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Ensure that the VRM, capacitors, and FPGA are all connected to these planes through multiple, low-inductance vias (Micro-vias, Vias-in-pad). Each via is part of the inductance of this path.
Remote Voltage Sensing:
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Must use differential sensing lines (V_SENSE+ / V_SENSE-), and the sensing connection point (Kelvin Connection) should be set at the “center” of the FPGA power pins, not at the output of the VRM.
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This requires that the differential lines be tightly coupled during routing, away from high-noise switching nodes (SW node) and inductors, to ensure that the controller can accurately sense the true voltage at the load end.
Chapter 5,
WEEKLY REPORT
Verification and Conclusion—From “Feeling” to “Seeing”
After the design is complete, how do we verify our transient response performance?
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Time Domain Verification: Use dedicated load step tools (Load Stepper) or a self-built MOSFET switching circuit to apply a fast current step on the FPGA’s power rail. Use a high-bandwidth oscilloscope and probes to directly measure the amplitude of voltage droop and recovery time.
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Frequency Domain Verification: Use a vector network analyzer (VNA) with specialized PDN probes to directly measure the impedance curve of our designed PDN across a wide frequency band and compare it with our initially calculated Z_target.
Conclusion:
Designing load point power supplies for modern FPGAs and SoCs has long surpassed the passing line of “stable operation”. It is an extreme performance competition unfolding between picoseconds and milliohms. Its core design philosophy has evolved from traditional, feedback compensation-based “passive defense” to proactive planning based on target impedance and COT control.
This requires us to:
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Think like a system architect: Lead the entire design with target impedance (Z_target) as the guiding principle.
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Layout like an RF engineer: Treat every segment of PCB traces as a distributed element, fighting against parasitic inductance and capacitance.
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Select materials like a materials scientist: Deeply understand the frequency characteristics, ESR, ESL, and DC bias effects of different capacitors.
As the “electronic component sales team”, we provide not only industry-leading COT controllers, DrMOS power stages, and low ESR capacitors. We offer a knowledge system and design methodology that maximizes the potential of these high-performance components. Join us to inject a truly powerful “heart” into your next high-performance computing platform.
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