To debug ARM, you must follow the ARM debugging interface protocol, and JTAG is one of them. During simulation, IAR, KEIL, ADS, etc., all have a common debugging interface, and RDI is one of them. So how do we convert RDI to the ARM debugging protocol (JTAG)? There are two approaches:
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Write a service program on the computer that parses RDI commands from IAR, KEIL, and ADS into the relevant JTAG protocol, then send your target board through a physical conversion interface (note that this conversion is only an electrical physical layer conversion, similar to RS232). H-JTAG is an example of this. The hardware of H-JTAG is merely a physical level conversion interface, so it is quite simple. The h-JTAG software installed on the computer is the service program mentioned earlier, responsible for the protocol conversion.
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Create a board that directly receives debugging commands from software such as IAR, KEIL, and ADS, and this board performs the RDI to JTAG protocol conversion. This is how JLINK works.
From the above, it can be seen that H-JTAG is slower because it performs protocol conversion through software, but the hardware is simple. In contrast, JLINK generally comes with a powerful CPU for hardware protocol conversion, making it hardware complex but faster.
Basic Principles of JTAG
JTAG (Joint Test Action Group) is an international standard testing protocol (IEEE 1149.1 compatible). The standard JTAG interface consists of four lines—TMS, TCK, TDI, and TDO, which correspond to mode selection, clock, data input, and data output lines, respectively.
JTAG has two main functions, or two major categories:
1) One is used to test the electrical characteristics of chips and detect whether there are issues with the chips;
2) The other is for debugging various chips and their peripheral devices; a CPU containing a JTAG Debug interface module can access the CPU’s internal registers, devices on the CPU bus, and registers of built-in modules through the JTAG interface as long as the clock is normal. This article mainly introduces the debugging function.
Analysis of JTAG Principles
In simple terms, the working principle of JTAG can be summarized as: defining a TAP (Test Access Port) inside the device to test and debug internal nodes using specialized JTAG testing tools. First, let’s introduce the basic concepts and content of boundary scan and TAP.
Boundary Scan
The basic idea of Boundary-Scan technology is to add a shift register unit close to the chip’s input/output pins, known as the Boundary-Scan Register.
When the chip is in debug mode, the boundary-scan register can isolate the chip from the peripheral input/output. Through the boundary-scan register unit, observation and control of the chip’s input/output signals can be achieved. For the chip’s input pins, signals (data) can be loaded into the pin through the connected boundary-scan register unit; for the chip’s output pins, the output signals on the pin can also be