January 1, 20251 st 9 afternoon, at the Institute of Computing Technology, Chinese Academy of Sciences, the Advanced Computing Systems Research Center invited Professor He Hu and his team from the School of Integrated Circuits, Tsinghua University, successfully organized a series of academic reports themed “Ventus: A High-performance Open-source GPGPU Based on RISC-V and Its Vector Extension”.
This report comprehensively and deeply introduced Tsinghua University’s latest research achievements in the open-source GPGPU “Chengying” (Ventus) project, covering the GPGPU top-level design concepts, microarchitecture implementation, cache and memory subsystems, AI acceleration units, software compilers, toolchains, differential verification frameworks, and full-stack technical details of FPGA prototype verification.The main content of the series of reports is as follows:
1. Overview of the Ventus GPGPU Project (Project Overview): Professor He Hu, an associate professor at the School of Integrated Circuits, Tsinghua University, delivered the opening speech. He systematically introduced the original intention of the Ventus (Chengying) GPGPU project, key technical points, team development history, future research goals, and open-source community construction plans. Professor He briefly introduced the complete layout of the Chengying GPGPU in terms of instruction set (ISA), hardware architecture, compilers, simulators, and verification tools.
2. GPGPU Design Philosophy, Instruction Set, and Core Architecture (GPU Design Philosophy & ISA & Core Architecture) Doctoral student Ma Mingyuan from the School of Integrated Circuits, Tsinghua University, elaborated on the essence of GPGPU as a hardware multithreaded SIMD processor from the three parallel dimensions of modern processor instructions, data, and threads. He discussed in detail the core issues that need to be addressed in instruction design for SIMT (Single Instruction Multiple Threads) hardware and explained how the Ventus GPGPU constructs a fully functional GPGPU base based on the RISC-V Vector extension. The report further introduced several important design aspects of the Ventus ISA, as well as the Chisel open-source version microarchitecture implementation of core components such as the CTA scheduler, Core pipeline, and warp scheduler.
3. Ventus GPGPU Cache Subsystem and MMU Design (Ventus GPGPU Cache Subsystem and MMU) Doctoral student Sun Haonan from the School of Integrated Circuits, Tsinghua University, systematically introduced the cache subsystem and memory management module (MMU) design of the Chengying GPGPU. This design, under the RISC-V RVWMO memory model, adopts a cache coherence mechanism (RCC) based on release consistency guidance, balancing low latency and global correctness through the division of fast-path and robust-path. At the microarchitecture level, the L1D cache employs a hierarchical MSHR/WSHR/SMSHR and RTAB mechanism to achieve efficient non-blocking access; the atomic unit is tightly coupled with the L2 cache and extends TL-UH/reduced TL-UL channels to efficiently handle LR/SC and AMO operations. In the virtual memory part, the system is configured with a multi-level TLB and combines auxiliary jump structures to optimize page table traversal. Test data shows that this design controls the MMU overhead between 15%–25% while ensuring functional correctness, achieving over 95% L1 DTLB hit rate and over 85% L2 TLB hit rate.
4. A Multi-Precision Reusable Tensor Core Design (A Multi-Precision Reusable Tensor Core Design) Doctoral student Liu Wei from the School of Integrated Circuits, Tsinghua University, introduced the next-generation multi-precision tensor core (Tensor Core) designed specifically for AI workloads optimization in the Ventus GPGPU. This design supports various emerging data precisions from FP16 to INT4, as well as MX FP8/FP6/FP4, and is compatible with the OCP MX fine-grained quantization standard, achieving flexible and efficient matrix multiplication calculations. The Tensor Core adopts a hardware resource reuse design, efficiently supporting multiple precision switches and saving hardware area through dynamic reuse of heterogeneous multipliers. Architecturally, it combines double buffering and pipelining design, matching memory and computing capabilities closely, approaching the theoretical performance optimum of the Roofline model. This unit also supports multi-size MMA (Matrix Multiply-Accumulate) calculations (e.g., m16n16k16, m32n8k32) and integrates 2:4 sparse acceleration technology. Benchmark tests show that after integrating the Tensor Core, the instruction count and execution cycle count for specific workloads achieved significant optimizations of 69.1% and 68.4%, respectively.
5. GVM: A Practical Differential Verification Framework for Ventus GPGPU (GVM: A Practical Differential Verification Framework) Master’s student Xie Wenxuan from the School of Integrated Circuits, Tsinghua University, introduced the GVM (GPU Verification Model) framework. GVM is an instruction-level hardware-software collaborative differential verification framework for the Ventus GPGPU, which performs differential comparison between RTL (DUT, Design Under Test) and a customized instruction set simulator (ISS, Instruction Set Simulator) (REF, Reference Model). This framework addresses the verification challenges posed by out-of-order completion of GPGPU instructions by introducing a software ROB (Re-Order Buffer) under SIMT semantics and performing state comparisons. GVM operates at the warp granularity, supporting configurable retire instruction sets, comparison ranges, on-demand single-instruction comparisons, and Next-PC checks, and provides specialized handling for special semantics such as barriers, instruction stitching, and atomic operations. GVM has been successfully integrated into the Ventus software stack and can be directly called by OpenCL programs, effectively discovering several subtle bugs and significantly shortening the debugging cycle.
6. Toolchain Design for Ventus OpenGPGPU (Toolchain Design for Ventus OpenGPGPU) Engineer Kong Li from Tsinghua University introduced the design philosophy of the Ventus GPGPU toolchain. This toolchain includes core modules such as Compiler, Runtime, Driver, and Simulator, implementing OpenCL API interfaces and unified device control, and supports custom instructions and GPGPU component simulation. The functional stability of the toolchain has passed core verification through OpenCL-CTS (overall pass rate of about 85%) and benchmark test sets such as Rodinia, achieving full-process support from hardware verification to upper-layer program execution.
7. Hands-on Demo: Ventus GPGPU Simulation and FPGA Verification (Hands-on Demo) The final segment of the tutorial was a practical demonstration. Master’s student Wang Yaohan from Tsinghua University provided entry-level guidance for developers new to the Chengying GPGPU through an interactive Jupyter webpage, detailing the component structure of the project’s open-source repository (https://github.com/THU-DSP-LAB/ventus-env), the complete method for self-deploying the project, and the process and functional settings for running OpenCL programs on functional/timing/RTL simulators.
In previous sharing sessions, the Chengying team also shared other related topics:
8. Triton and OpenCL Compilers for Ventus GPGPU (Triton and OpenCL Compilers for Ventus GPGPU) This topic introduced the software stack design of the Chengying GPGPU, focusing on the implementation considerations of the OpenCL compiler and the design of the Triton AI operator library compiler. Currently, the Chengying GPGPU supports the OpenCL 2.0 profile and has passed over 85% of the OpenCL conformance test. At the same time, it analyzed the challenges of OpenCL compared to CUDA in terms of ecosystem and high-performance function libraries, proposing that the Triton-based AI operator library is an effective path to solve the current dilemma. The Chengying GPGPU can leverage the Triton ecosystem to enable ML engineers to develop efficient operators in a more user-friendly manner. Zhaosong Technology (enterprise) has utilized its long-term accumulation in MLIR and LLVM compilation technology to create a complete end-to-end solution for the Chengying GPGPU, from MLIR+LLVM model/operator library to hardware instruction translation optimization.
9. FPGA-based Ventus GPGPU Implementation and Verification. The team built a two-level FPGA verification platform: the basic level is a self-contained verification system deployed on the VCU128 FPGA, with a MicroBlaze soft core as the control unit, integrating the Ventus GPGPU core (1SM 8warp 16thread@50MHz), loading test programs via JTAG interface; the advanced level demonstrates the actual running effects of key tests such as mainstream neural network inference on FPGA, forming a complete hardware verification solution from core function verification to practical application acceleration.
This series of reports systematically showcased Tsinghua University’s full-stack research layout and in-depth exploration in the field of RISC-V open-source GPGPU, receiving widespread attention and active discussion from nearly 100 students, teachers, and experts from the Institute of Computing Technology, Chinese Academy of Sciences.
The Advanced Computing Systems Research Center of the Institute of Computing Technology, Chinese Academy of Sciences, was established in September 2011. The center is currently mainly engaged in hardware-software co-design for emerging workloads such as big data and artificial intelligence, open-source chips, and open-source computer systems. Center website: https://acs.ict.ac.cn.
