This series of articles will delve into the CDC issues, introducing CDC handling, CTS, and CDC timing constraints. Interested readers are encouraged to follow.The previous article in this series, 【Series】Detailed Explanation of Digital IC/FPGA Cross-Clock Domain Issues (1) Synchronous and Asynchronous Clocks, introduced synchronous/asynchronous clocks and the limitations of fully synchronous designs. This article will provide an in-depth introduction to the phenomenon of metastability in digital circuits and the causes of metastability during the data sampling process.In digital circuits, the essence of the metastability problem is that a flip-flop may enter an “uncertain” state (x state) due to input timing violations. Importantly, the impact of this unknown state can propagate to subsequent circuits, potentially causing the entire system to fail. Therefore, the metastability problem can be viewed as a critical state issue under low tolerance conditions. To illustrate, one can think of the current state of the circuit as a “ball at the peak” in the diagram below. Assuming the slope and the ball are perfectly smooth, the ball appears to be at rest at the peak, but random disturbances can cause the ball to slide down to positions 1 or 2 in the diagram.
In digital circuits, the aforementioned non-ideal external factors may include temperature, radiation, or electrostatic discharge. Positions 1 and 0 in the diagram represent the circuit’s output levels of 0/1, while the ball can be likened to a bistable device.In FPGA or ASIC design, flip-flops are a type of edge-triggered bistable device that can achieve state retention, state switching, and provide digital circuits with “memory capability.”Due to the physical delays of the logic gates that make up the flip-flop, sufficient time windows must be reserved to ensure accurate sampling of the input signal. This time window corresponds to the Setup Time and Hold Time in the diagram below.
In which scenarios does metastability occur? Metastability can occur when data or reset control signals are outside the sampling window, such as in the following situations:
- Asynchronous Signal Detection
- Cross-Clock Domain Data Transfer
- Reset Circuit
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Autumn Recruitment Sample Questions:
1. Which of the following is NOT a problem introduced by asynchronous circuits? ( ).
A. STA cannot check timingB. Logic errorsC. GlitchesD. Metastability
Answer: A. STA can only check synchronous clocks.
2. When signals cross clock domains, metastability occurs. Its failure is related to which factors?? ( ) .
A. The flip-flop output signal transition rate at the signal transmitterB. The clock frequency of the flip-flop at the signal transmitterC. The clock frequency of the flip-flop at the signal receiverD. The number of synchronous flip-flopsAnswer: A, B, C, D.Previous Highlights:【Series】Detailed Explanation of Digital IC/FPGA Cross-Clock Domain Issues (1) Synchronous and Asynchronous Clocks【Autumn Recruitment】Huawei Logic Special Session, Logic/Digital IC/FPGA – Interview Points Analysis (3) STA Static Timing Analysis【Autumn Recruitment】Huawei Logic Special Session, Logic/Digital IC/FPGA – Interview Points Analysis (1) HDL Basics and Timing Constraints【Autumn Recruitment】Huawei Logic Special Session, Logic/Digital IC/FPGA – Interview Points Analysis (2) SV Basics