1. FPGA Development Series
2. Digital Signal Processing Series
3. FIR Filter Series
1. FPGA Development Series
Application of Ultrasonic Doppler Frequency Shift Demodulation Based on FPGA and MATLAB (Part 1)
Application of Ultrasonic Doppler Frequency Shift Demodulation Based on FPGA and MATLAB (Part 2)
Image Processing Based on FPGA: Image Grayscale Processing
Image Processing Based on FPGA: 3x3_5x5 Operator Template Design
Image Processing Based on FPGA: Median Sorting in 3x3_5x5 Operator Template
AXI Protocol: AXILite Development and Design
FFT Function Verification of FPGA and MATLAB
Learning Vivado with Xiao Huihui: Configuration Mode of 7 Series FPGA – Main SPI Four-Way (x4)
Learning Vivado with Xiao Huihui: Configuration Data File Format and Configuration Timing Steps of 7 Series FPGA
Learning Vivado with Xiao Huihui: MultiBoot and Fallback Function for Updating Firmware of 7 Series FPGA
Learning Vivado with Xiao Huihui: PCIe XDMA for Remote Updating of FPGA Firmware
FPGA Popular Science Series: Everything Can Be FPGA, What is FPGA?
FPGA Popular Science Series: The Three Stages of FPGA: Invention, Expansion, Accumulation
How is Slack Calculated in Vivado Timing Reports? How to Optimize Timing?
Vivado Timing Optimization – Constraint for Asynchronous Clock Groups set_clock_groups
Detailed Explanation of TX Path Clock of GTY in UltraScale+ FPGA – Taking 40G ETH MAC IP as an Example
DDR4 Traversal Read/Write Test Based on FDMA and AXI4 Interface
Xilinx UltraScale+ DDR4 Project Development (Part 3) – DDR4 Device Selection and MIG IP Configuration
Xilinx UltraScale+ DDR4 Project Development (Part 2) – Clock Network of DDR4 MIG
Xilinx UltraScale+ DDR4 Project Development (Part 1) – IP Interface Signals of DDR4 MIG
Solution for Multi-Lane Alignment Abnormality of Serdes in UltraScale+ FPGA
What to Do When Xilinx Vivado Tool Stuck in Synthesis?
In Vivado + ModelSim Co-Simulation, How to Modify the DO File to Achieve Independent Operation of Simulation Code and Synthesis Code?
Low-Speed Interface Project: UART Development (Part 1) – UART
Low-Speed Interface Project: UART Development (Part 2) – UART Transmit and Receive Modules
Low-Speed Interface Project: UART Development (Part 3) – FIFO Implementation of UART Data Loopback Test
Low-Speed Interface Project: UART Development (Part 4) – UART Implementation of Reading and Writing Control of FPGA Internal AXILITE Registers
Low-Speed Interface Project: UART Development (Part 5) – QT Implementation of UART Register Read/Write Tool
Low-Speed Interface Project: UART Development (Part 6) – Zynq Series PS-PL Side UART Implementation of Shared Axilite Internal Register Read/Write
Low-Speed Interface Project: UART Development (Part 7) – How to Implement Adaptive Baud Rate UART Function in FPGA Project
Low-Speed Interface Project: UART Development (Part 8) – How to Achieve Online Upgrade of Zynq via PS Side UART (Part 1)
Low-Speed Interface Project: UART Development (Part 9) – How to Achieve Online Upgrade of Zynq via PS Side UART (Part 2)
Low-Speed Interface Project: UART Development (Part 10) – Custom PL UART Implementation of Zynq Online Upgrade Based on EMIO
Low-Speed Interface Project: UART Development (Part 11) – Zynq PL Side UART Online Upgrade
Low-Speed Interface Project: UART Development (Part 12) – PL Read/Write Test of PS Side DDR3 Based on FDMA and ZYNQ
Aggregation Forwarding and Cross-Clock Domain Processing Based on AXI Stream PKG Data Mode
128-bit Cross-Connect Packet Interface of 40G/50G Ethernet Subsystem
How to Achieve Custom Frequency Clock of FPGA via AXILITE Interface
Classic Never Goes Out of Style: Ping-Pong Operation for ADC Data Sampling Transmission
How to Automatically Obtain FPGA Compilation Time in Vivado for FPGA Version Update
Configuration of SPI Devices Inside FPGA via AXILITE Interface (Part 1)
Configuration of SPI Devices Inside FPGA via AXILITE Interface (Part 2)
How to Obtain Delay Data from FPGA Internal Die to Pin? How to Generate and Export Pin Delay Files in Vivado?
Vivado Timing Constraint Learning Series: Physical Constraints and Timing Constraints in Design Constraints
Vivado Timing Constraint Learning Series: Common Concepts in Timing Constraints (Clock, Setup Time and Hold Time, Timing Margin, etc.)
Vivado Timing Constraint Learning Series: System Synchronization, Source Synchronization, and Self-Synchronization Timing Models
Vivado Timing Constraint Learning Series: Serdes and Xilinx GT Structure in Self-Synchronization
Vivado Timing Constraint Learning Series: Clock Architecture in Xilinx 7 Series
Vivado Timing Constraint Learning Series: Clock Architecture in Xilinx U/U+ Series
Vivado Timing Constraint Learning Series: What is the Difference Between MMCM and PLL? Which Clock Configuration Should Be Chosen? How to Optimize BUFG/BUFH?
What Types of Xilinx High-Speed Transceivers Are There? What Line Rates Do They Support? What Are the Functional Differences?
2. Digital Signal Processing Series
Digital Signal Processing Learning Series: How Are Signals Defined and Classified? Concepts of Gain and Attenuation? Distortion and Measurement Methods?
Digital Signal Processing Learning Series: Noise in Signal Processing and Processing Methods
Digital Signal Processing Learning Series: Structure of Signal Processing Systems and Signal Processing Methods
Digital Signal Processing Learning Series: Analog-to-Digital Converter (ADC)
Digital Signal Processing Learning Series: Digital-to-Analog Converter (DAC) and Spurious-Free Dynamic Range (SFDR)
Digital Signal Processing Learning Series: Basic Concepts of Digital Signal Processing
Digital Signal Processing Learning Series: Time Domain and Frequency Domain, Vectors, MATLAB
Digital Signal Processing Learning Series: General Knowledge of Signals
Digital Signal Processing Learning Series: Classic Signals
Digital Signal Processing Learning Series: Basic Operations of Signals
Digital Signal Processing Learning Series: Discrete-Time Fourier Transform (DTFT)
Digital Signal Processing Learning Series: How to Understand Time Domain Sampling and Frequency Domain Extension?
Digital Signal Processing Learning Series: Terminology Decibel (dB)
Digital Signal Processing Learning Series: Sampling, Quantization, and Encoding
Digital Signal Processing Learning Series: Detailed Explanation of Sampling in A/D
Digital Signal Processing Learning Series: Encoding in A/D (Fixed Point and Floating Point Representation)
Digital Signal Processing Learning Series: Cutoff Frequency and Stopband Attenuation in Anti-Aliasing Filters
Digital Signal Processing Learning Series: How to Choose Sampling Frequency?
Digital Signal Processing Learning Series: How to Understand Systems and Their Classification?
Digital Signal Processing Learning Series: Linear Time-Invariant Systems (LTI)
Digital Signal Processing Learning Series: Frequency Invariance of Linear Time-Invariant Systems (LTI)
Digital Signal Processing Learning Series: How to Understand Z-Transform?
Digital Signal Processing Learning Series: What is the Use of the Zero-Pole Plot of a System?
Digital Signal Processing Learning Series: Frequency Response of LTI Systems: Magnitude and Phase Response
Digital Signal Processing Learning Series: Example of Zero-Pole Plot and Magnitude Response of a Reverb System
Digital Signal Processing Learning Series: How to Calculate Convolution?
Digital Signal Processing Learning Series: How to Understand the Meaning of Convolution?
Digital Signal Processing Learning Series: MATLAB Example of Radar Distance Measurement
Digital Signal Processing Learning Series: Basics of Digital Filters
Digital Signal Processing Learning Series: How to Classify Digital Filters?
Digital Signal Processing Learning Series: Frequency Domain Performance and Time Domain Performance of Digital Filters
Digital Signal Processing Learning Series: Design Elements of Digital Filters
Digital Signal Processing Learning Series: How to Implement High-Pass, Band-Pass, and Band-Stop Filters Using Low-Pass Filters?
Digital Signal Processing Learning Series: DC Offset Calibration in ADC Sampling Process
3. FIR Filter Series
FIR Filter Series: Basics of FIR Filters
FIR Filter Series: Principle of Window Function Method
FIR Filter Series: Performance of Various Window Function Methods in MATLAB?
FIR Filter Series: How to Use Window Function fir1 in MATLAB to Generate Filter Coefficients?
FIR Filter Series: FIR Filtering of Audio Signals in MATLAB
FIR Filter Series: What Structures Are There for FIR Filters?
FIR Filter Series: Quantization Effects of FIR Filter Coefficients in MATLAB
FIR Filter Series: Two Methods for Generating FIR Filter Coefficients in MATLAB
FIR Filter Series: Two Methods for Generating FIR Filter Coefficients in MATLAB
FIR Filter Series: Joint Simulation Verification Platform for FIR IP of MATLAB + Vivado + ModelSim (Part 1)
FIR Filter Series: Joint Simulation Verification Platform for FIR IP of MATLAB + Vivado + ModelSim (Part 2)
FIR Filter Series: Joint Simulation Verification Platform for FIR IP of MATLAB + Vivado + ModelSim (Part 3)