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This article mainly discussesthe two modes of FIFO in FPGA
FIFO stands for First-In, First-Out, which is a “first in, first out” buffer. In FPGA design, it is a very basic and crucial component/module, whose core function can be summarized as: serving as a data buffer and bridge to resolve issues of speed mismatch and clock domain synchronization between data senders and receivers.
The following image shows the FIFO in Intel (Altera) FPGA development tool: Quartus
Normal Mode (Read Request Mode): “rdreq” serves as the read request signal, when high, the data output is the first data;
Show-Ahead Mode (Read Acknowledge Mode): “rdreq” serves as the read acknowledgment signal, when rdreq is low, the data output is the first data; when high, the data output is the second data.
The following image shows the FIFO in AMD (Xilinx) FPGA development tool: Vivado
Standard FIFO is the normal FIFO in Intel FPGA.
First Word Fall Through is the ahead mode in Intel FPGA.
Normal Mode Waveform
Data is output immediately after the rising edge samples rdreq or rden as high.
Show-Ahead Mode Waveform
When there is data in the FIFO, the first data is output directly. After the rising edge samples rdreq or rden as high, the second data in the FIFO is output immediately.
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