According to industry conventions, “small FPGAs” typically refer to FPGA products with a logic density of less than200K SLC (System Logic Cells). In December 2019, Lattice(Lattice) launched the industry’s firstNexus™ platform, which has set a “new benchmark” for small FPGAs with its five key features: low power consumption, high performance, high reliability, advanced security, and ease of use. It is regarded as an important update in low-power FPGA technology.
Building on this, from 2019 to 2022, Lattice developed products based on theNexus™ platform, includingCrossLink-NX,Certus-NX,CertusPro-NX, andMachXO5-NX, providing developers with greater architectural flexibility and system-level integration capabilities to meet the needs of general and secure control applications.
Lattice Nexus™ platform
In 2024, with significant improvements in “advanced interconnect,” “optimized power and performance,” and “leading security performance,” the “next-generation small FPGA platformNexus™ 2 and the first device series based on this platform,Certus™-N2 general FPGA, further strengthens Lattice’s leading position in the small FPGA field.
As a leading supplier of low-power programmable devices globally, Lattice’s commitment to the small FPGA product field has not stopped. Recently, new, highI/O density device options have been provided forCertus™-NX FPGA andMachXO5™-NX FPGA series, once again becoming a hot topic in the industry.
A new breakthrough with a fresh combination
The newly launchedCertus-NX andMachXO5-NX devices are also based on theNexus™ FPGA platform, offering richer device choices, higherI/O density, performance, and system integration, as well as stronger stability and security, which are the core competitive advantages exhibited by the new products across multiple dimensions—enabling developers to precisely match different application needs, especially in power-constrained artificial intelligence, industrial, communication, server, and automotive applications, which typically have more stringent requirements for low power consumption, small size, high3.3V I/O density, and security features in FPGA devices.
Lattice launches new Certus-NX and MachXO5-NX devices
Compared to similar FPGAs, the new devices can increase the number ofI/O per square millimeter by up to2 times, while supporting3.3V I/O and1.5Gbps differentialI/O, ensuring faster and more stable data transmission. Moreover, the device size can be reduced by up to3 times, making it very suitable for compact circuit board layouts.
The new devices can reduce power consumption by up to4 times, which not only simplifies the product’s thermal design but also effectively extends the battery life of powered devices. The integrated flash memory within the device can increase the boot configuration speed by up to12 times, significantly accelerating system boot time. More importantly, the design does not require power sequencing control, reducing external circuitry and bill of materials(BOM) costs.
In terms of stability and security, the new devices can reduce the soft error rate by up to100 times, significantly enhancing the reliability of safety-critical applications. The built-in single error correction(SEC) and storage block ECC can both reduce the impact of soft errors and effectively resist single event upsets(SEU), further ensuring the stable operation of the system.
Differentiated design under a unified platform
Although both are based on theNexus™ platform, considering that different vertical segments have their own unique requirements, Lattice tends to favor “differentiated design under a unified platform” in product planning. For example,CertusPro-NX has enhanced aspects such as power consumption design, system bandwidth, edge processing, reliability, and packaging diversity; while compared toCrossLink-NX, theCertus-NX FPGA has removed theMIPI hard core to increase the number ofI/O, which is very helpful for some customers usingPCIe for general control.
Next, let us review the core characteristics of different product series over time.
Opening a new “vision” in machine vision
With the increasing popularity of edge artificial intelligence(Edge AI), intelligent vision technology that provides critical safety and obstacle avoidance capabilities for autonomous driving and robotics is becoming essential. In the future, intelligent vision systems will continue to rely on deep learning models and neural networks to enhance image analysis and recognition capabilities, utilizing reinforcement learning and autonomous adaptive learning to enable systems to continuously learn and improve from their environment and adapt to new scenarios and tasks.
To this end,CrossLink™-NX FPGA has been designed with28nm FD-SOI technology and optimized FPGA architecture, reducing the soft error rate by100 times, with power consumption reduced by up to75%. The two4 channelMIPI D-PHY transceiver hard cores operate at a rate of2.5G/Lane (10Gbps/PHY), achieving approximately2 times the performance compared to peers. Using a small size WLCS package, with a minimum size of4mm2, it is nearly10 times smaller than similar products, ensuring a highly scalable, low-cost, low-power solution that provides flexible interconnect and supports variousI/O standards and protocols.
Continuously challenging the limits of power and performance
The Certus-NX series FPGA is Lattice’s second FPGA product developed based on theNexus™ platform in 2020, primarily targeting a wide range of communication, computing, industrial, and automotive applications. TheFD-SOI process, small size packaging, flexibleI/O, andPCIe Gen2, Gigabit Ethernet interfaces, and advanced encryption features are the most notable product tags of theCertus-NX series.
In terms of logic resources,Certus-NX can have up to65K logic cells,3.3 Mb of embedded memory,128 18×18 multipliers, and380 programmableI/O. It supports differentialI/O of up to1.5Gbps, which is 70% faster than similar FPGAs, and also supports5Gbps PCIe,1Gbps GigE, and1066Mbps DDR3 memory interfaces.
Compared to similar competitors,Certus-NX series sizes are reduced by up to3 times, with a minimum size of36mm2, and theI/O density can increase by up to2 times; power consumption can be reduced by up to4 times; when configuring the device via SPI memory, the speed can reach up to12 times that of similar FPGA competitors at 8-25 ms.
This series is manufactured using28 nm FD-SOI technology, with the soft error rate(SER) reduced by up to100 times, and built-inSEC and storage block ECC forSEU protection, enhancing the system reliability for safety-critical applications.
Opening up a new world for mainstream FPGAs
The advanced general FPGA CertusPro-NX is primarily launched to meet the innovative application needs in intelligent systems for data collaborative processing,5G communication infrastructure’s high bandwidth signal bridging, andADAS systems’ sensor interface bridging. Therefore, in design,CertusPro-NX FPGA supports up to8 programmableSERDES channels, with speeds up to10.3 Gbps, providing the highest system bandwidth in its class(twice that of similar competitors FPGAs).
At the same time, to meet the demand for stable data co-processing in edge AI and machine learning applications,CertusPro-NX FPGA supports up to100K logic cells, making it the device with the highest logic density among allNexus™ based FPGAs. Its on-chip memory capacity is also about65% higher than that of other similar FPGAs, and it is currently the only low-power FPGA that supports the LPDDR4 DRAM storage standard. In addition,CertusPro-NX has added ultra-efficient DSP modules and both small and large internal memory modules based on a programmable architecture to support low-latency data processing in artificial intelligence and machine learning applications.
Enhanced security control FPGA
MachXO5-NX FPGA is the fifth device of theNexus™ platform and the sixth device of the MachXO series, with core competencies as “enhanced security control FPGA” including “more logic and memory resources,” “stable programmableI/O,” “industry-leading security performance,” and “leading low power consumption and stability.”
MachXO5-NX FPGA has a logic cell density of100K and more DSP modules and ADC modules, providing more powerful computing and control capabilities. Compared to FPGAs with similar densities,MachXO5-NX offers up to2.9 times the embedded memory and up to36 times the dedicated user flash memory, easily coping with the trend of increasing design complexity. At the same time, the integrated flash memory supports single-chip solutions, enabling instant boot operations and reliable field updates, as well as multiple configuration images.
With the increasing security threats, security has become increasingly important in any system design.MachXO5-NX supports AES256 bitstream encryption andECC256 bitstream authentication to protect the integrity of system designs. The security engine can also be used at runtime to protect data exchange between the system and the FPGA. In contrast, similar FPGA competitors currently cannot provide security features during operation.
How do these FPGAs create value?
Continuously introducing more flexibility and functionality into compact, low-power devices to help developers meet strict thermal, interconnect, and size constraints in various innovative designs has always been Lattice’s mission. Therefore, let us take some time to look at how these new devices create value:
In industrial automation systems, highI/O density, low static and dynamic power FPGAs are ideal choices for space-constrained applications(such as control modules and sensor aggregation Hub). The devices support single-rail power-up and are compatible with any power sequencing, simplifying power architecture andPCB layout; the instant boot configuration feature achieves sub-millisecond startup, which is crucial for reliable responses in latency-sensitive environments.
In automotive applications, enhanced reliability and robust soft error mitigation mechanisms(such as ECC protected storage blocks and configuration refresh) are core requirements for functional safety compliance in systems such as advanced driver assistance systems(ADAS), battery management systems(BMS), and in-vehicle network architectures. The compact size of these FPGAs allows seamless integration into space-constrained electronic control units(ECUs), while meeting the stringent performance and thermal design requirements under automotive-grade operating conditions.
In edge AI applications(such as smart cameras or smart IoT nodes), the combination of low power consumption, high-speedI/O, and secure configuration enables real-time data processing at the edge. Developers can deploy custom logic for AI preprocessing, encryption, or sensor fusion while maintaining a compact hardware size.
In communication applications(such as switches, network function virtualization, and edge computing), higher3.3V I/O, optimized logic density and package size, combined withPCIe Gen2 functionality, make these FPGAs ideal solutions for offloading CPU loads. Bitstream validation and encryption features can meet the increasing security demands.
In server deployments, these small-sized secure FPGAs provide hardware roots of trust, secure boot, and fast encryption during real-time data transmission or processing, ensuring data integrity and confidentiality. HighI/O density supportsPCIe Gen 2, Ethernet, and other multi-gigabit interfaces, achieving low-latency data transmission and parallel processing; the compact form factor can be integrated into dense server blades and network cards while adapting to the typical stringent power and thermal constraints of large-scale and edge data centers.
Conclusion
Small-sized FPGAs are by no means synonymous with “performance compromise,” but rather open up new value spaces in low power consumption, high reliability, and strong security dimensions through architectural optimization, process innovation, and scenario-based design. In the future, as the demand for “small yet powerful” intelligent devices becomes increasingly urgent, Lattice’s deep technical accumulation and scenario insights in the small FPGA field will continue to drive more industry breakthroughs beyond physical limitations and performance bottlenecks.
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