Exploring Low Power Design Techniques

Before making a decision, hesitation may be necessary. However, once a decision is made, one should move forward without looking back.

― ― Dazuo Ishikawa

Unknowingly, I have written several articles on the topic of SoC power consumption, so let’s summarize them.

  • SoC Design Power Consumption — Introduction

  • SoC Design Power Consumption — Clock Gating

  • SoC Design Power Consumption — DVFS

  • SoC Design Power Consumption — Q Channel

  • SoC Design Power Consumption — Multi Voltage

  • SoC Design Power Consumption — Power Gating

  • SoC Design Power Consumption — RTL/netlist Power Calculation

  • SoC Design Power Consumption — RTL Power Calculation (Part 2)

  • SoC Design Power Consumption — IR Drop

  • SoC Design Power Consumption — IR Drop (Part 2)

  • SoC Design Power Consumption — Electromigration (EM)

  • SoC Design Power Consumption — UPF

There are also two articles on the power design framework of the ARM architecture.

  • ARM Series — PCSA (Part 1)

  • ARM Series — PCSA (Part 2)

There are various methods for low power design. At the system level, there are dynamic voltage scaling (DVS) techniques and power gating; at the next level, one can implement dynamic frequency scaling (DFS) and clock gating; further down to logic implementation, there are many RTL coding rules, such as operand isolation, storage unit isolation, and so on.From another perspective, let’s recall the formula for switch power consumption. Power consumption is proportional to the square of the voltage, proportional to the switching rate (which can be broken down into two issues: clock frequency and switching count), and proportional to the load. Continuing this line of thought, voltage can be adjusted through voltage regulation and power switches; around the clock, switching can be managed; around the flipping, unnecessary flips can be reduced through encoding; finally, how can we reduce the overall load inside the chip? By using more advanced processes, haha.One of the most frequently asked questions regarding power consumption is, “What methods are available for low power design in chips?” Or in other words, “With so many low power design methods, which ones should I choose?” Today, I’d like to offer some thoughts.First, we should start from the source. Personally, I recommend the principle of minimal design, which means not adding unnecessary functions. This is different from design redundancy. I agree with adding redundancy to ensure certain reliability or scalability. Back to the power consumption issue, if power consumption itself does not significantly affect the chip, or has a minimal impact, then there is no need to incorporate low power design methods.So how do we determine whether low power design is necessary? I think we can start from several perspectives:

  • Is the system’s power supply constrained? For example, some IoT chips are powered by dry batteries or button batteries, which have strict requirements for battery life. Similarly, non-contact RF cards.

  • Will power consumption affect usage? For example, some chips are used in environments where heat dissipation is difficult; excessive power consumption may raise the ambient temperature, leading to excessive leakage and ultimately failure to converge.

  • Will power consumption affect chip performance? For example, data shows that for every 15°C increase in local temperature within a processor chip, the delay in that area increases by about 10%-15%; similarly, with a temperature rise of 10-15°C, the local resistance increases by 10%, thus the corresponding IR drop also increases by about 10%.

  • Will power consumption cause the BOM cost of the entire system to be unacceptably high? For instance, server processors may require higher-end heatsinks/fans or water cooling to address excessive power consumption and heat issues.

  • Will power consumption affect chip reliability? For instance, the IR and electromigration issues mentioned in the article.

  • And so on.

If you clarify the chip’s usage scenarios and working environments, the questions of whether to implement low power design or what level of low power design is needed will become clear. Consider this a starting point for discussion; everyone is welcome to share their thoughts~~

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