Recently, I have been reading “The Art of Hardware Architecture”, and this blog post is also derived from the content in the book.
With the advancement of technology, low-power design has become increasingly important.As a digital front-end designer, let’s take a look at how to reduce power consumption at the RTL level.
In large-scale ASIC design, once the RTL design is completed, at least 80% of the total power consumption is already determined.The backend process cannot fix microarchitecture issues, and both microarchitecture and RTL coding style have a significant impact on dynamic and static power consumption.Let’s discuss several ways to reduce power consumption at the RTL level.
Encoding and Decoding of State Machines
Among various state machine encodings, Gray code is the most suitable for low-power design. This is because it only changes one flip-flop at a time during state transitions, and Gray code-encoded state machines also eliminate the risk of glitches that depend on state combination equations.The image above compares binary encoding and Gray code encoding.
Binary Number Representation
In most applications, signed numbers are represented using two’s complement, but during the transition from sign-magnitude to two’s complement, many bits change. In contrast, changes in signed numbers are less, as shown in the figure for the two’s complement and signed number representation of 0 and 1.The choice of representation should depend on the specific application context.
Gated Clock
Previous blog posts have detailed gated clocks, but here I will mainly explain gated clocks from the coding perspective.During the coding process, consider whether backend tools can incorporate gated clocks in the environment settings.Here’s an example, let’s look at the following RTL code and its logical implementation:
This implementation results in 32 mux2s, but if we change it to the following description, some backend tools may recognize that load_cond is shared by 32 registers, thus replacing 32 mux2s with a single gated clock, as shown below:
This method of reorganizing gated signals and data paths should be considered in power reduction.
One-Hot Multiplexer
Multiplexer implementation can be achieved through case statements, if statements, and state machines. The commonly used multiplexer employs binary encoding. If the inputs to the mux are multi-bit buses, it will produce significant switching activity, thus generating power consumption.
However, if the case conditions are encoded using one-hot encoding, the output will be faster and more stable, and initially, it can mask the unselected buses, achieving low power consumption.
Multiplexers are generally present in digital circuit designs, so avoiding or masking the occurrence of spurious transitions can effectively reduce power consumption.
These two encoding and implementation methods are shown in the diagram below:
Eliminating Unnecessary Transitions
Without setting a default state, bus data often undergoes meaningless transitions.If the transitioned data is not sampled, it is redundant, and removing such transitions can significantly reduce power consumption.As shown below:
This design reads all input signals, but ultimately only one output will be used. Therefore, by using an AND gate to eliminate unnecessary transitions, we can save some power consumption, as shown below.
Resource Sharing
In designs with many arithmetic clouds, avoid the corresponding logic operations from appearing in multiple locations, as using duplicate logic increases area and power consumption, as shown in the diagram below:
Using Ripple Counters to Reduce Power Consumption
Ripple counters can be used to reduce power consumption, but because each register has propagation delays, the high significant bits will change later than the low significant bits.
During the clock progression, counters may produce incorrect values due to glitches, especially when the most significant bit changes, which can have the worst impact.For example, in a four-bit counter, when transitioning from 0111 to 1000, it will briefly show 0111, 0110, 0100, 0000, 1000.
Ripple counters pose a significant challenge for STA since each stage generates a new clock domain, requiring STA tools to handle more clock domains, thus consuming more time.
Using low active enable signals for ripple counters can prevent glitches from occurring.The counter’s circuit is triggered on the positive edge, and when the counter’s signal is stable, readings should be taken during the low level of the clock to ensure that the data read is stable.
However, the high level duration of the clock must be at least as long as the maximum ripple cycle of the counter to avoid the clock signal receiving data while the ripple process is still ongoing. The improved method is shown in the diagram below:
Bus Inversion
When the Hamming distance (the number of differing bits between two numbers) between current data and next data is greater than N/2, the next data is inverted before transmission to reduce the number of bits that change on the bus, known as bus inversion coding.
This technique is very effective in reducing the number of transitions on large buses.Thus, during data transmission, an extra control bit must be added to indicate whether the transmitted data has been inverted.Below is an example of data after bus inversion, where the total transitions reduced from 54 to 32.
High Activity Networks
Distinguish between high activity networks and low activity networks, and place them deeper within the logic cloud.For example, changes in x1…xn have a lower frequency, while Y is a high activity network. Therefore, divide the logic cloud into two parts, one for Y=0 and the other for Y=1. Typically, the size of the two new logic clouds will be reduced.
Enabling and Disabling Logic Clouds
When operating large-scale logic cloud computations, it is often necessary to enable them only when needed. In the diagram below, trigger B has an enable signal, but trigger A does not turn off since the outputs are used elsewhere in the design, leading to wasted energy in the entire logic cloud.One improvement method is to move the enable signal to the front of the logic cloud, disabling it when the logic cloud is not needed, as shown below:
