In the field of edge AI, the contradiction between “flexibility” and “efficiency” has always been a core bottleneck that the industry struggles to overcome. The algorithm iteration speed of large models far exceeds the hardware update cycle. Highly specialized architectures (such as traditional DSA) can achieve high energy efficiency but quickly become ineffective when switching algorithm paradigms (e.g., from CNN to Transformer). On the other hand, generalized architectures (such as traditional DSP) can adapt to various algorithms but are inefficient in processing the core matrix operations of large models. In November 2025, Arm Technology released the “Zhouyi” X3 NPU IP, which provides a systematic solution to this paradox through a deep fusion architecture of DSP and DSA, redefining the design logic of edge AI hardware.
The architectural dilemma of traditional NPUs has become increasingly prominent with the popularization of Transformer large models. Early edge NPUs were mostly based on DSA (Domain-Specific Architecture) designs, optimized for convolution operations in CNN networks, performing excellently in perception tasks such as face recognition and image classification. However, when large models transitioned to the Transformer architecture, the core attention mechanism, matrix multiplication, and LayerNorm operations significantly differ from the computational logic of CNNs, leading to a “functional mismatch” in the hardware units of traditional DSA architectures. Circuits originally optimized for convolution cannot efficiently handle the tensor computations of Transformers, resulting in a sharp drop in computing power utilization, sometimes falling below 30% in certain scenarios. In contrast, pure DSP (Digital Signal Processor) architectures can adapt to various algorithms through general instructions, but when faced with the high-density matrix operations of Transformers, they require multiple rounds of instruction scheduling, achieving only 1/5 to 1/3 of the energy efficiency of specialized DSAs, making it difficult to meet the power consumption constraints of edge devices.
The breakthrough of the “Zhouyi” X3 lies in constructing a hybrid architecture of “Wenwu Collaboration”: using the AIFF hardware engine (DSA) as “Wu” to efficiently handle high-frequency, fixed core computations; and the TEC processor (DSP) as “Wen” to undertake flexible and variable auxiliary computations, with both working together through a unified instruction set. Specifically, the AIFF engine, as a dedicated acceleration unit, has hardware optimizations for the core tasks of the Transformer architecture—such as directly implementing matrix multiplication (which accounts for over 70% of the computational load of large models) and LayerNorm operations through circuits, completing tasks without software scheduling. In tests with the Llama2 7B model, the AIFF engine alone handled 85% of the computational load, achieving an energy efficiency ratio six times that of traditional DSP. The TEC processor focuses on the approximately 30% of “long-tail computations,” such as activation functions (GELU, Sigmoid) and dynamic control flows (conditional branches, loops), which can be more than four times the types of tensor computations. Relying on CPU/GPU heterogeneous processing would incur significant data transfer overhead, leading to overall performance bottlenecks. The X3 customizes 1200 AI-specific vector instructions for the TEC processor, allowing it to achieve an energy efficiency ratio of over three times that of general CPUs when handling flexible tasks, completely eliminating performance losses in “long-tail computations.”
More critically, the “Zhouyi” X3 addresses the efficiency challenges of traditional NPUs that rely on CPU scheduling through a dedicated hardware scheduler. Traditional edge NPUs require frequent CPU intervention to allocate computing power and synchronize data when processing multiple AI tasks in parallel (e.g., smart cockpit running voice interaction, fatigue monitoring, and environmental perception simultaneously), leading to CPU loads of 10% to 20%. This not only occupies application resources but can also cause task stuttering due to scheduling delays. The X3 implements scheduling logic directly through hardware circuits: the hardened scheduler can monitor the priority of each task in real-time (e.g., ADAS tasks have higher priority than entertainment tasks), computing power requirements, and data dependencies, autonomously completing power allocation and data synchronization without CPU intervention. Tests show that when processing four AI tasks in parallel, the X3’s resource usage on the main CPU is only 0.5%, and scheduling delays have been reduced from traditional microsecond levels to nanosecond levels, ensuring millisecond-level responses for high-priority tasks (such as environmental perception in automatic parking).
The practical effects of this architectural design have been fully validated in tests. In the Softmax operator tests, which are core to the Transformer model, through the collaborative optimization of the AIFF engine and TEC processor—where AIFF handles the basic computations of matrix operations and TEC processes flexible operations such as exponentiation and normalization—the X3 achieved a tenfold performance improvement, far exceeding the industry average optimization range of 3 to 5 times. In the full-process tests of the Llama2 7B large model, the X3’s multi-core computing power linearity reached 70% to 80% (i.e., four-core computing power is close to 3.2 times that of single-core computing power), while traditional NPUs typically have multi-core computing power linearity below 60%. This means that the X3 can efficiently handle larger-scale models through multi-core expansion.
From an industry perspective, the DSP+DSA fusion architecture of the “Zhouyi” X3 is not merely a simple “functional overlay” but is designed on demand based on edge AI scenarios. It avoids the “algorithmic fragility” of specialized architectures and addresses the “energy efficiency shortcomings” of generalized architectures, providing a flexible and efficient hardware foundation for the implementation of large models at the edge. As Dr. Shu Hao, head of Arm Technology’s NPU product line, stated: “This architecture balances ‘current efficiency’ and ‘future adaptability,’ ensuring that hardware is no longer a bottleneck for algorithm iteration but a support for innovation in edge AI.”