An Overview of the Bank Structure in Xilinx 7 Series FPGAs

The I/O interfaces of the Xilinx 7 series FPGAs are organized into several banks. Each bank shares the same power supply for its I/O pins and shares some resources.

Why Divide into Banks

  1. Dividing the I/O pins into different banks allows different pins to operate at different voltages. This enables the connection of circuits operating at various voltages without the need for voltage conversion, thereby enhancing the flexibility of circuit design.

  2. It has been said that this approach can reduce manufacturing costs, which in turn lowers the price of the FPGA.

  3. FPGAs have a large number of I/O pins, and typically, not all of them are used. In such cases, signals can be concentrated on a few banks while the remaining banks are powered down, thus reducing the power consumption of the FPGA.

  4. When designing banks, it is possible to tailor them for different usage scenarios. For example, the high range (HR) banks and high performance (HP) banks in the Xilinx 7 series.

HR Bank

As the name suggests, the Xilinx 7 series high range (HR) banks are generally numbered in the teens, such as 12, 13, and 14.

HR banks can support a wide voltage range: 1.2~3.3V.

HR banks are typically used for low-speed signal transmission and reception, such as FPGA configuration pins, SPI, reset signals, discrete signals, etc.

HP Bank

As the name suggests, the Xilinx 7 series high performance (HP) banks are generally numbered in the thirties, such as 33, 34, and 35.

HP banks can support a smaller voltage range: 1.2~1.8V.

HR banks are generally used for high-speed signal transmission and reception, such as DDR3. For even higher speeds, transceivers like GTP and GTX are required.

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