19.4
Analysis of DTC Module Block Diagram
19.4.1
Internal Registers of DTC
The MRA, MRB, SAR, DAR, CRA, and CRB are all internal registers of the DTC that cannot be accessed directly by the CPU. The values set in these internal DTC registers are placed in the SRAM area as transfer information. When an activation request is generated, the DTC reads the transfer information from the SRAM area and sets it in its internal registers. After the data transfer is complete, the contents of the internal registers are written back to the SRAM area as transfer information.
When using the DTC, we indirectly configure these internal DTC registers by configuring the transfer information.
19.4.2
Event Link
The DTC can generate an event link request upon completing a transfer request. However, when the transfer destination is an external bus, the event link request will be issued after the write buffer is completed, rather than after the actual transfer destination is completed.
19.5
DTC Transfer Modes
The DTC module supports three operational modes, lacking the repeat-block transfer mode compared to DMAC.
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Normal Mode:In normal mode, the DTC transfers a single data unit each time it receives an interrupt trigger. The data unit can be 1, 2, or 4 bytes. The transfer length can be set to [0,65535]. When the length is set to 0, the DTC will perform 65536 transfers instead of 0. After each transfer, the source and destination addresses can be individually set to fixed, incrementing, or decrementing. After each transfer, a 16-bit counter decrements. When the counter reaches 0, the DTC transfer will no longer be triggered by the interrupt source, and the CPU can be interrupted to notify that all transfers are complete.
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Repeat Mode:The repeat mode operates similarly to the normal mode, but the length is limited to integers within the range [1,256]. When the transfer counter reaches 0, the counter is reset to its configured value (length), the repeat area (source or destination address) is reset to its starting address, and the transfer will still be triggered by the interrupt.
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Block Mode:In block mode, the amount of data units transferred per interrupt can be set to integers within the range [1,256]. The number of blocks to be transferred (num_blocks) can also be configured as a 16-bit number, which can be set to [0,65535]. When the length is set to 0, the DTC will perform 65536 transfers instead of 0. After each block transfer, the repeat area (source or destination address) will reset to the original address, while the other address will increment or decrement to the next block.
19.5.1
Normal Transfer Mode
The Normal Transfer Mode allows for 1-byte (8-bit), 1 half-word (16-bit), or 1 word (32-bit) data transfers on a single activation source. The transfer count can be set from 1 to 65536 (0x10000). The source and destination addresses can also be independently set to incrementing, decrementing, or fixed. This mode allows for generating an interrupt request to the CPU when the specified count transfer ends.
The memory mapping for Normal Transfer Mode is shown in the figure below
19.5.2
Repeat Transfer Mode
The Repeat Transfer Mode allows for 1-byte (8-bit), 1 half-word (16-bit), or 1 word (32-bit) data transfers on a single activation source. The transfer source or destination of the repeat area must be specified in the MRB.DTS bit. The transfer count can be set from 1 to 256.
When the specified transfer count is completed, the initial values of the address registers specified in the repeat area are restored, the initial value of the transfer counter is restored, and the transfer is repeated. The other address register continuously increments or decrements or remains unchanged.
In Repeat Transfer Mode, when the transfer counter CRAL decrements to 0x00, the CRAL value is updated to the value set in the CRAH register. Therefore, the transfer counter does not clear to 0, and when the MRB.DISEL bit is set to 0, the interrupt request to the CPU is disabled. An interrupt request to the CPU will be generated when the specified data transfer is completed.
The memory mapping for Repeat Transfer Mode when the transfer source is the repeat area is shown in the figure below:
19.5.3
Block Transfer Mode
The Block Transfer Mode allows for single block data transfers on a single activation source. The transfer source or destination of the data block area must be specified in the MRB.DTS bit. The block size can be set from 1 to 256 bytes, 1 to 256 half-words (2 to 512 bytes), or 1 to 256 words (4 to 1024 bytes).
When the specified block transfer is completed, the initial values of the block size counter CRAL and the address register (SAR register when MRB.DTS=1 or DAR register when DTS=0) are restored. The other address register continuously increments or decrements or remains unchanged. The transfer count (block count) can be set from 1 to 65536. This mode allows for generating an interrupt request to the CPU when the specified count block transfer ends.
The memory mapping for Block Transfer Mode is shown in the figure below:
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To be continued
Recommended Reading
DMAC Module Block Diagram Analysis – Practical Guide to Renesas RA Series FSP Library Development (52)
DMAC/DTC: Direct Memory Access and Data Transfer – Practical Guide to Renesas RA Series FSP Library Development (51)
UART Redirection in Version 5.2.0 E2S – Practical Guide to Renesas RA Series FSP Library Development (50)