Welcome FPGA engineers to join the official WeChat technical group. During remote updates, sometimes dual images are needed to ensure the stability of the design. When updating the design, only one image is updated, while the other image has been tested and does not require updates before deployment. If an update fails, operations can be … Read more
Combining the previous articles into a PDF, the main directory is as follows: 1 HDMI Display Based on FPGA 1.1 Introduction to HDMI 1.2FPGA-based HDMI Interface Design 1.3 HDMI Timing Analysis 1.4FPGA-based 720P HDMI Display 1.4.1 HDMI Hardware Circuit Analysis 1.4.2 Project File Design 1.4.3 Establish Vivado Project 1.4.4 Create Project Files 1.4.5 Experimental Results … Read more
Welcome FPGA engineers to join the official WeChat technical group. I originally wrote an introduction to the preliminary debugging plan for high-speed transceivers, providing some initial debugging suggestions when encountering problems. However, I found that it involves many concepts. Explaining them one by one would make the article too lengthy. Therefore, I wrote a separate … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – China’s largest and best community for pure FPGA engineers. This article is mainly to casually record some content related to dedicated clock pins of FPGA encountered while creating constraint files for my current FPGA project, aimed … Read more
01 Introduction This article discusses the current level of FPGA development in China, the companies that are doing well, and the factors to consider for domestic FPGA alternatives. Some content and data are referenced from the internet and official websites. If there are inaccuracies, I hope to discuss and learn from experts. FPGA, The Universal … Read more
Welcome FPGA engineers to join the official WeChat technical group Clickthe blue textto follow us at FPGA Home – the best pure engineer community in China Detailed Explanation of Xilinx RapidIO Core 1. Overview of RapidIO Core The design standard for the RapidIO core comes from the RapidIO Interconnect Specification rev2.2, which supports three modes: … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the largest and best pure FPGA engineering community in China. In the past month, the FPGA market has been booming. In this article, we will briefly examine the three latest released FPGAs from Xilinx, Intel, and … Read more
Introduction: From this article onwards, we will successively introduce the clock resource architecture of Xilinx 7 series FPGA. Mastering clock resources is very important for both FPGA hardware design engineers and software design engineers. This chapter provides an overview of the 7 series FPGA clocks, compares the differences between the 7 series FPGA clocks and … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the largest pure FPGA engineering community in China. Introduction: When we conduct FPGA schematic and PCB design, we involve the pin definitions and package-related information of FPGA chips. This article provides relevant references for the Xilinx … Read more
EETOP focuses on chips and microelectronics, click on the blue text above to follow us. EETOP EETOP Chuangxin Network (Yite Chuangxin): A well-known domestic veteran electronic engineer community and semiconductor industry portal website (1.5 million members) www.eetop.cn bbs.eetop.cn blog.eetop.cn edu.eetop.cn EETOP compiled from allaboutcircuits.In the past month, the FPGA market has been thriving. In this … Read more