Speeding Up DDR Adaptation on Rockchip SoC Platforms! (Issue 6: RK3399)

Speeding Up DDR Adaptation on Rockchip SoC Platforms! (Issue 6: RK3399)

The global storage market is undergoing a structural adjustment, and the shortage of DDR chips has become a common challenge in the electronics industry. Rockchip’s mainstream SoC platforms (RK3588, RK3576, RK3566, etc.) leverage multi-type DDR support capabilities, along with three core strategies of “tuning, mixing, and switching,” to provide practical solutions for numerous partners, helping … Read more

Rockchip SoC Platform DDR Adaptation Accelerated!

In the past year, the shortage of DDR chips has become a common challenge faced by the electronics industry, leading not only to rising prices of end products and increased R&D costs but also causing project delays, particularly affecting consumer products. As a chip company deeply engaged in the smart terminal field, Rockchip’s mainstream SoC … Read more

Common Commands for DDR and NPU on AllWinner MR536

In the AllWinner MR536 Tina5 Linux system environment, the commonly used debugging commands on the board are as follows:1. Mount debugfs (the /sys/kernel/debug directory will depend on this) mount -t debugfs none /sys/kernel/debug 2. Get DDR frequency cat /sys/kernel/debug/clk/clk_summary | grep ddr After execution, it may return the following content: pll-ddr 5 5 0 2784000000 … Read more

FPGA Hardware Development – DDR Design

FPGA Hardware Development - DDR Design

1. Hardware Circuit Design (Basic Assurance) Power Supply and Ripple Control The core power supply (e.g., 1.2V for DDR4) should be independently powered, paired with a capacitor array of 10μF + 0.1μF, with ripple control within ±5%; Termination resistors (ODT) should be placed close to the DDR chips, with matched impedance (typically 50Ω/60Ω) to reduce … Read more

Bus – DDR

Bus - DDR

We will provide a detailed introduction to the very important DDR bus. This is a comprehensive introduction from basic concepts to technical details. 1.What is the DDR bus? The DDR bus is an electronic channel used in computers to transfer data, addresses, and control commands between the memory controller (usually located within the CPU) and … Read more

DDR Configuration of Renesas RZ/G2L MPU (1)

DDR Configuration of Renesas RZ/G2L MPU (1)

The RZ/G2L microprocessor is equipped with a Cortex®-A55 (1.2GHz) CPU, a 16-bit DDR3L/DDR4 interface, a 3D graphics acceleration engine with Arm Mali-G31, and a video codec (H.264). Additionally, this microprocessor features a variety of interfaces, such as camera input, display output, USB 2.0, and Gigabit Ethernet, making it particularly suitable for entry-level industrial human-machine interfaces … Read more

Comparison Table of SK Hynix eMMC, UFS, DDR, LPDDR, HBM, eMCP, and uMCP Storage Chips

Comparison Table of SK Hynix eMMC, UFS, DDR, LPDDR, HBM, eMCP, and uMCP Storage Chips

1. DDR2. LPDDR3. GDDR4. HBM5. eMMC, UFS Part No. Model Name Density Mono-Density PKG Size PKG Type Spec Product Status H26M41208HPR EE510 8GB 64Gb 11.5x13x0.8mm FBGA eMMC 5.1 MP H26M41204HPR EE510 8GB 64Gb 11.5x13x0.8mm FBGA eMMC 5.1 MP H26M74002HMR EG510 64GB 128Gb 11.5x13x1.0mm FBGA eMMC 5.1 MP H26M62002JPR EG510 32GB 128Gb 11.5x13x0.8mm FBGA eMMC 5.1 … Read more

A Method for Absolute Memory Address Location in MCUs

A Method for Absolute Memory Address Location in MCUs

Follow+Star Public Account Number, don’t miss out on exciting contentSource | Renesas Embedded EncyclopediaIn a previous article titled “How to Add Version Information to MCU Projects?” we used absolute addresses: #define VERINFO_ADDR_BASE (0x0800FF00) // Address for storing FLASH const char Software_Ver[] __attribute__((at(VERINFO_ADDR_BASE + 0x00))) = "Software: 1.0.0"; const char Compiler_Date[] __attribute__((at(VERINFO_ADDR_BASE + 0x40))) = "Date: … Read more