Bus – DDR

We will provide a detailed introduction to the very important DDR bus.

This is a comprehensive introduction from basic concepts to technical details.

1.What is the DDR bus?

The DDR bus is an electronic channel used in computers to transfer data, addresses, and control commands between the memory controller (usually located within the CPU) and the memory modules (commonly referred to as memory sticks, such as DDR4, DDR5).

You can think of it as a “highway” connecting the CPU and memory, where data travels like vehicles on this highway. The width of this “highway” (bus width), speed (frequency), and efficiency (data transfer rate) directly determine how quickly data can be accessed and processed by the CPU, thus having a significant impact on the overall system performance.

Its full name is Double Data Rate Synchronous Dynamic Random Access Memory Bus, which breaks down as follows:

• Double Data Rate: This is the core of DDR technology.

• Synchronous: This means the memory operates in sync with the system bus clock.

• Dynamic: This requires constant refreshing to maintain data.

• Random Access: This allows for arbitrary read and write access to any address.

• Bus: This is a collection of signal lines.

2. Core Working Principle: Double Data Rate

The most core and revolutionary technology of the DDR bus is that it transfers data on both the rising and falling edges of the clock signal.

• Comparison to SDR: Before DDR, there was SDR SDRAM (Single Data Rate). It only transferred data on the rising edge of the clock signal.

• How DDR Works: DDR memory transfers data once on the rising edge of the clock signal and then again on the falling edge. This way, at the same physical clock frequency, the data transfer rate reaches twice that of SDR.

For example, a DDR memory with a core physical clock frequency of 100MHz has an effective data transfer frequency of 200MHz. This is the origin of the “double rate”.

https://media.geeksforgeeks.org/wp-content/cdn-uploads/20230316165653/DDR-vs-SDR.png

3. Main Components of the DDR Bus

The DDR bus is not a single wire, but consists of three different sets of buses:

1.Data Bus

• Function: Responsible for the actual data transfer, it is “bidirectional” (it can write data to memory and read data from memory).

• Bus Width: Typically 64 bits. This is why we often say “dual-channel”—two 64-bit channels combine to form a 128-bit channel, doubling the data throughput. ECC memory adds an additional 8 bits for error checking, making it 72 bits.

2.Address Bus

• Function: The CPU uses it to tell the memory “which address data do I want to access”. It is “unidirectional” (from the controller to the memory).

• Characteristics: The address bus and command bus are usually multiplexed to reduce the number of pins.

3.Control/Command Bus

• Function: Transmits various control signals, such as read/write commands, chip select signals, clock enable, etc., directing the memory to perform specific operations (such as read, write, refresh, etc.). It is also “unidirectional” (from the controller to the memory).

4. Development and Generational Changes of DDR

DDR technology has been iteratively developed, with each generation bringing higher speeds, lower voltages, and larger capacities.

Generation	Characteristics	Voltage	Prefetch Width	Representative Rate
DDR	First generation DDR, core technology innovation	2.5V	2n-prefetch	DDR-266, DDR-400
DDR2	Higher rates, lower power consumption	1.8V	4n-prefetch	DDR2-800
DDR3	Further popularization, becoming mainstream for many years	1.5V	8n-prefetch	DDR3-1600
DDR4	High frequency, low latency, high capacity	1.2V	8n-prefetch	DDR4-3200
DDR5	Revolutionary changes, speed doubled	1.1V	16n-prefetch	DDR5-6400+

Key Upgrade Points:

• Prefetch: Each generation increases the prefetch width, allowing more data to be prepared for transfer on the rising and falling edges of the clock, which is key to improving rates.

• Voltage: The voltage continues to decrease, meaning lower power consumption and heat generation.

• Rate: Each generation’s peak data transfer rate has significantly increased compared to the previous generation. DDR5 even introduces the concept of dual 32-bit subchannels, further enhancing concurrency efficiency.

5. Important Technical Parameters and Concepts

1.Frequency

• Core Clock Frequency: The basic frequency at which the memory physically operates.

• Effective Data Transfer Rate: Due to DDR technology, the effective rate is twice the core frequency. The 3200 in “DDR4-3200” refers to 3200 MT/s.

2.Bandwidth

• Definition: The total amount of data that the bus can transfer in a unit of time, which is the ultimate measure of memory performance.

• Calculation Formula: Bandwidth = (Transfer Rate × Bus Width) / 8

• Example: The bandwidth of a single DDR4-3200 memory (with a bus width of 64 bits) is:(3200 MT/s × 64 bit) / 8 = 25600 MB/s = 25.6 GB/s. If it is dual-channel, then multiply by 2, reaching 51.2 GB/s.

3.Timing

• Definition: A series of parameters that describe memory operation latency, usually represented by a string of numbers, such as CL-tRCD-tRP-tRAS (for example, 16-18-18-38).

• CL Value: CAS Latency, which is the most critical timing parameter. It indicates the number of latency cycles from issuing a read command to starting to receive data.

• General Rule: The higher the frequency, the larger the timing (more latency cycles). Low timing and high frequency are equally important and are the focus of memory overclocking enthusiasts.

6. Applications of the DDR Bus

The DDR bus is the cornerstone of modern computing devices, widely used in:

• Personal Computers

• Servers (typically using memory with ECC checking)

• Workstations

• Laptops

• Smartphones (using smaller-sized LPDDR, which is based on DDR technology but focuses on low power consumption)

• Graphics Cards (using specialized GDDR, based on DDR but with ultra-high bandwidth, less sensitive to latency than DDR)

Conclusion

The DDR bus is a crucial data channel between the CPU and memory, and its double data rate working mechanism is the source of high performance. Through multiple generations of technology iterations (DDR1→DDR5), it has continuously broken through in frequency, bandwidth, capacity, and energy efficiency, directly driving the development of the entire computing industry. Understanding the DDR bus is essential for comprehending computer architecture, evaluating system performance, and making hardware selections.