Board Overview

The VPX638 is a 6U VPX general signal processing platform based on the KU115 FPGA and C6678 DSP. This platform utilizes a Xilinx Kintex UltraScale series FPGA (XCKU115) as the main processor to perform complex data acquisition, playback, and data preprocessing. It employs a TI multicore floating-point DSP TMS320C6678 to execute signal processing algorithms.

The main processor XCKU115 is equipped with two sets of 72-bit DDR4 SDRAM to achieve ultra-large capacity data caching, with a data cache bandwidth of up to 2400MHz. The KU115 FPGA can interact with other boards through the backplane. The KU115 FPGA is connected to two FMC+ HPC interfaces, supporting the expansion of two FMC daughter cards. The TI Keystone series multicore floating-point DSP processor TMS320C6678 supports 2GByte of DDR3 data cache and one Gigabit Ethernet interface. Data exchange with the main FPGA is conducted via SRIO or EMIF.The board also supports a microcontroller for health management, reporting status information via the IPMB bus. It includes a CPLD chip for controlling the power-up sequence.This board is designed for VPX air-cooled compatible conduction cooling architecture, featuring excellent vibration resistance, thermal performance, and unique environmental protection design, making it suitable for applications in aerospace, aviation, and marine environments.

Technical Specifications

1. Standard 6U VPX specification, compliant with VITA46;

2. Onboard high-performance FPGA processor: XCKU115-2FFVF1924I 1)

• Two sets of 72-bit DDR4 SDRAM, each with a capacity of 4GByte;
• Two QSPI Flash chips, totaling 1Gbit capacity, for FPGA loading;
• Two FMC+ HPC interfaces;

3. Onboard a high-performance DSP processor: TMS320C6678

• One set of 64-bit DDR3 SDRAM, total capacity 4GByte;

• One Nor Flash chip, capacity 512Mbit, for DSP loading;

• One 4Gbit Nand Flash for storing a small amount of parameter data;

• Front panel supports one RJ45 Gigabit Ethernet interface, with one GbE output;

• FPGA and DSP interconnection: 1 SRIO x4@5Gbps/lane;

4. VPX Backplane Interconnection

• VPX P1: Supports 4 lanes of x4 SRIO connected to KU115 FPGA;

• VPX P2: Supports PCIE X8 connected to KU115 FPGA;

• VPX P3: Supports LVDS X8 connected to KU115 FPGA;

• VPX P4: Supports one GBE, connected to DSP;

• VPX P5: Supports 4 RS422 interfaces, 16 GPIO outputs, and 8 GPIO inputs;

5. Front Panel J30 Interface

• Supports one FPGA download, one MCU download, and one CPLD download interface;

• Supports one DSP download interface;

6. Physical and Electrical Characteristics

• Board dimensions: 160 x 233mm2)

• Board power supply: 6A max@+12V (±5%)

• Cooling method: Air cooling + conduction cooling

7. Environmental Characteristics

• Operating temperature: -40°~ +85°C,

• Storage temperature: -55°~ +125°C;

• Operating humidity: 5%~95%, non-condensing

Software Support

Provides low-level interface drivers;

Application Scope

1. Software-defined radio;

2. Radar and baseband signal processing;