Understanding the JTAG Protocol for ECU Debugging

In the ECU software development process, software debugging or testing often involves the JTAG interface, which is used through the JTAG protocol with emulators/debuggers such as JLink, ST-LINK, and Lauterbach for online debugging of software programs. Although many use it daily, not everyone is familiar with it. Therefore, this article intends to provide a brief introduction.

1 Overview of the JTAG Protocol

JTAG (Joint Test Action Group) is an international standard testing protocol that defines how to communicate with devices that have boundary scan capabilities, such as microcontrollers, FPGAs, and DSPs. JTAG allows access to the internal registers, memory, and pins of these devices, as well as programming them with new software. JTAG can also link multiple devices together and control them from a single interface.

The formal name of the JTAG protocol is IEEE 1149.1, which is an important technology in the field of electronics and digital design. It is a standardized method for testing and debugging integrated circuits (ICs) and printed circuit boards (PCBs). First, let’s understand its history:

JTAG was established in the mid-1980s to develop a method for verifying designs and testing printed circuit boards after manufacturing. Before the development of JTAG, testing and debugging electronic circuits was a time-consuming and expensive process, as engineers had to manually probe and test each pin on the circuit board, which was not only slow but also prone to errors. The creation of JTAG aimed to provide a standardized interface for testing and debugging electronic circuits, using a set of special Test Access Ports (TAP) that allow engineers to interact with the circuit and perform various testing and debugging tasks.

The first version of the JTAG standard was released in 1990 and quickly gained popularity among engineers and manufacturers. In the following years, the JTAG standard underwent multiple revisions and updates, adding new features and functionalities to make testing and debugging easier and more efficient.

source: https://www.corelis.com/education/tutorials/jtag-tutorial/what-is-jtag/

• The establishment of JTAG: In 1985, representatives from leading companies in the electronics industry, including Texas Instruments, IBM, Intel, and HP, formed the Joint Test Action Group. The main goal of this group was to create a standardized method for testing and debugging electronic systems, as traditional methods for testing these systems became increasingly complex and challenging.
• Early development and contributions: Key contributors to the early development of the JTAG protocol included Ken Parker from Texas Instruments, who proposed the concept of accessing multiple pins of an IC or PCB for testing through a single standardized interface. David Brownell from IBM made significant contributions to the design of the JTAG state machine, which plays a crucial role in controlling test operations and transitions.
• Introduction of the JTAG standard: In 1987, the Joint Test Action Group officially released the JTAG standard, namely IEEE 1149.1. This standard, titled “Standard Test Access Port and Boundary Scan Architecture,” provides a comprehensive framework for implementing the JTAG protocol in electronic devices. The JTAG standard defines the necessary signals and their functions, state machine operations, and boundary scan testing techniques.
• Rapid adoption and industry impact: The JTAG protocol quickly gained recognition in the electronics industry due to its numerous advantages. By providing a standardized testing method, JTAG greatly simplified the testing process for complex systems. It allows engineers to perform non-intrusive testing and debugging, even when physical access to individual pins is difficult or impossible. As a result, JTAG has become an indispensable part of the design, manufacturing, and testing processes for various electronic products.
• Evolution and expansion: With continuous technological advancements, the JTAG standard has evolved to meet the changing needs of the industry. Other standards and extensions have been introduced to enhance the capabilities of JTAG. For instance, IEEE 1149.4 addresses analog testing capabilities, while IEEE 1149.6 focuses on testing challenges in high-speed digital systems.
• Integration into industry standards: JTAG has been integrated into various other industry standards to further expand its range of applications and advantages. Notably, it has become part of IEEE 1500, which focuses on testing intellectual property (IP) cores within integrated circuits.

2 Architecture of the JTAG Protocol

The IEEE-1149.1 JTAG standard outlines the behavior of IC scan logic to ensure seamless interaction between components, systems, and test tools. Integrated circuits (ICs) contain logical units called boundary scan cells, located between the system logic and the signal pins that connect to the printed circuit board (PCB). These cells provide different testing functionalities, with some serving as inputs, others as outputs, and some having bidirectional capabilities.

The architecture of the JTAG protocol aims to provide a standardized method for testing and debugging integrated circuits (ICs) and printed circuit boards (PCBs). It consists of several key components that work together to facilitate efficient and non-intrusive testing of complex digital systems.

The main elements of the JTAG architecture include:

1. Test Access Port (TAP): The core of the JTAG architecture is the Test Access Port (TAP), which is a digital state machine used to control access to the internal components of the Device Under Test (DUT). It manages the data flow and control signals between the external testing device and the internal circuits of the DUT. The Test Access Port consists of four mandatory signals and an optional fifth signal:

• Test Clock (TCK): The clock signal that synchronizes data transfer between the testing device and the DUT.

• Test Mode Select (TMS): The control signal that determines the state transitions of the TAP state machine.

• Test Data Input (TDI): The bidirectional data signal used to input test data into the DUT.

• Test Data Output (TDO): The bidirectional data signal used to output test data from the DUT.

• Test Reset (TRST) (optional): The optional signal used to reset the TAP.

2. JTAG State Machine: The Test Access Port contains a state machine that manages the operations of the JTAG protocol. The state machine defines the different states that the TAP can be in and the transitions between these states. Each state corresponds to a specific operation, allowing the TAP to perform various functions during testing and debugging. The main states of the JTAG state machine are as follows:

• Test Logic Reset (TLR): The initial state after power-up or test reset, where the TAP remains in a stable state.

• Run Test/Idle (RTI): The TAP is in an idle state, waiting for instructions or test data.

• Select-DR-Scan (SDR): The state where the TAP is ready to shift data into or out of the DUT’s data register.

• Capture-DR (CDR): The state that captures input data to be shifted into the DR.

• Shift-DR (SDR): The state where data is shifted into or out of the DR.

• Exit1-DR (EDR1): The state where the TAP exits the Shift-DR state, preparing for the next operation.

• Exit2-DR (EDR2): The state where the TAP exits the Shift-DR state after the last bit has been shifted out.

3. Boundary Scan Register: The boundary scan register is one of the fundamental functionalities of the JTAG architecture. This register can be used to test the interconnections (networks) between different ICs on the PCB. It consists of input (bypass) and output (capture, shift, and update) units for each pin of the DUT. Boundary scan testing helps detect faults related to open circuits, short circuits, and other connectivity issues.

4. Instruction Register (IR) and Data Register (DR): The Instruction Register (IR) and Data Register (DR) are part of the JTAG architecture, helping to communicate and control the internal components of the DUT. The IR is used to select and control various operations, such as reading and writing data from internal registers, while the DR is used for data shifting during testing and programming.

3 JTAG Protocol Instructions

IEEE-1149.1 specifies specific instructions that must be followed to fully comply with JTAG requirements. To achieve JTAG compliance, devices must adopt and implement these instructions.

• EXTEST: The EXTEST instruction is used for interconnection testing. When activated, it connects the boundary scan register to the TDI and TDO, effectively putting the device into “external” test mode. In this mode, the boundary scan output units drive test data to the device pins, while the input units capture data from these pins. This instruction is critical for boundary scan testing.
• SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction is similar to EXTEST but allows the boundary scan device to maintain its task/function mode while still linking the boundary scan register to TDI and TDO. Using the SAMPLE/PRELOAD instruction, the boundary scan register can be accessed via data scanning while the device continues to operate. This feature is beneficial for preloading data into the boundary scan register without interrupting the device’s functional behavior, preparing it for subsequent execution of the EXTEST instruction.
• BYPASS: The BYPASS instruction establishes a direct connection between TDI and TDO through a single-bit register, bypassing the longer boundary scan register of the device, hence the name. BYPASS offers significant advantages in shortening the boundary scan chain by excluding devices that are not needed for the current operation. Devices receiving the BYPASS instruction maintain their task/function mode while allowing seamless serial data flow to subsequent devices in the chain.

4 JTAG Protocol TAP Controller

According to the IEEE-1149.1 standard, the TAP controller operates as a finite state machine with 16 states, guided by the Test Clock (TCK) and Test Mode Select (TMS) signals, with state transitions controlled by the TMS state on the rising edge of TCK. The state machine contains two analog paths that facilitate the capture and/or updating of data by scanning the instruction register (IR) or data register (DR), as shown below:

Each state in the JTAG state machine has two exits, with all transitions controlled by a single TMS signal sampled on TCK. The two main paths facilitate setting or retrieving information from the device’s data register or instruction register. The specific data register accessed (e.g., BSR, IDCODES, BYPASS) depends on the value loaded into the instruction register.

5 JTAG Connector and Pinout

The JTAG connector, also known as the JTAG header or JTAG port, is the physical connector used to establish a connection between a device or PCB and the JTAG interface. These connectors aid in testing, debugging, and programming devices using the JTAG protocol. Depending on their size, pin count, and application, there are several different types of JTAG connectors:

• 20-pin JTAG connector.
• 16-pin OCDS JTAG connector.
• 14-pin JTAG connector.
• 10-pin JTAG connector (ARM JTAG connector).
• Custom JTAG connectors.
• Surface-mount JTAG connectors.
• Flywire JTAG connectors.

Taking the 20-pin JTAG connector as an example, the 20-pin JTAG connector is the most widely used. As the name suggests, it has 20 pins arranged in two rows of 10 each. This type of connector is commonly used in traditional JTAG applications and can be found on many development boards and evaluation platforms. It provides a standard interface for JTAG communication and is compatible with most JTAG programmers and debuggers. The pin definitions are as follows:

6 How the JTAG Protocol Works

The operation of the JTAG protocol is to provide a standardized method for testing and debugging ICs and PCBs. It allows engineers to access and control the internal components of devices using the Test Access Port (TAP) and a defined set of states in the state machine. The following briefly describes how JTAG debugging from a PC works and runs code with breakpoints. The debugging process involves the following steps:

• Connect the JTAG hardware interface to the JTAG interface of the target device.
• Establish communication between the PC and the JTAG interface using the TCK, TMS, TDI, and TDO pins.
• Set the TAP to the desired state, such as Select-DR-Scan (SDR), to access and manipulate the internal registers of the device.
• Install the appropriate debugging software on the PC to connect to the target device via the JTAG interface.
• The debugging software allows you to read and write data to internal registers, set breakpoints, halt the processor, and perform other debugging operations.

Once the PC is connected to the target device via the JTAG interface, you can use JTAG to load code into the device’s memory. After loading the code, you can execute it like any other program. When using breakpoints, the debugging software communicates with the processor via the JTAG interface and instructs it to stop execution at a specific memory address (the breakpoint). When the processor reaches the breakpoint, it halts execution, allowing you to inspect the program state, memory contents, and register values, enabling you to analyze the program’s behavior and find errors or bugs in the code.

source: https://silo.tips/download/trace32-documents-ide-user-interface-ide-users-guide-1

7 Conclusion

In summary, the JTAG protocol has a wide range of applications in the electronics and embedded systems fields, with some key applications as follows:

For the automotive industry, it is mainly used in ECU development, with core functions for software flashing and debugging, such as the use of debuggers (Jlink, Lauterbach, and UDE) in ECU low-level software development. That concludes this brief introduction to JTAG. For more content related to ECU software development, please stay tuned for future articles.

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