Hello everyone, I am Chip Language. Today, let’s dive into the world of chip cultivation—from design to mass production, chips must go through numerous challenges: Tape-Out is the foundation, packaging testing is the tribulation, and yield is the ascension KPI… The fate of engineers is to protect the chips while sacrificing their hair for merit.
Semiconductor Jargon World Episode 1: The Storm of Tape-Out
[Scene: Chip Language rushes into a café holding a stack of design blueprints, Silicon Speech is scratching his head in front of a computer]
Chip Language: (breathless) Brother Silicon! My chip design is complete! I heard the next step is called… TO? This abbreviation sounds like “kick out”?
Silicon Speech: (pushing up his glasses) TO stands for Tape-Out, which translates to “流片” (Tape-Out), meaning sending the design to the wafer fab to make the chip. It’s like handing in your college entrance exam paper to the printing factory—if it’s printed wrong, you might have to repeat three years!
Chip Language: (covering his wallet) How much will that cost? I haven’t saved enough for my milk tea fund this month…
Silicon Speech: (sneering) Want to save money? Try MPW! It stands for Multi-Project Wafer, like carpooling! You can share your design with other companies on the same wafer to split the cost.
Chip Language: (eyes sparkling) Then I want to buy a “seat”! Is SEAT the second-class seat on a high-speed train?
Silicon Speech: (facepalming) SEAT refers to the area you occupy on the wafer! The smaller the area, the cheaper it is. But the rich choose FULL MASK— they book the entire “luxury car” to enjoy the mask exclusively!
Chip Language: (suddenly slamming the table) Wait! The wafer fab said there’s a Shuttle bus next week? Do I have to take a bus to deliver the design?
Silicon Speech: (holding back laughter) Shuttle is a regular tape-out service! Like a subway schedule, if you miss this bus, you have to wait three months. By the way, what Process Node are you using? 7nm or 5nm?
Chip Language: (with confidence) Process node? I choose the subway Line 1 node! After all, 7nm has a larger station distance than 5nm, so it’s less likely to miss the stop!
Jargon Science
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TO (Tape-Out): A milestone when chip design is completed and handed over for manufacturing, similar to submitting architectural blueprints to a construction team.
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MPW (Multi-Project Wafer): A shared wafer manufacturing service among multiple companies to reduce costs, suitable for small batch validation.
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FULL MASK (Full Mask): Exclusive use of an entire photomask set, high cost but controllable cycle, suitable for mass production.
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Shuttle (Shuttle Service): A scheduled tape-out period organized by the wafer fab, requiring advance “ticket grabbing”.
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SEAT (Wafer Seat): The area allocated to a single design in MPW, charged by area.
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Process Node (Process Node): Such as 7nm/5nm, the smaller the number, the higher the transistor density, but the development difficulty increases exponentially.
Semiconductor Jargon World Episode 2: The Philosophy of Pizza and Strawberries
[Scene: Chip Language rushes into the cafeteria holding a wafer, while Silicon Speech is deep in thought over a plate of fried eggs]
Chip Language: (excited) Brother Silicon! I just snagged a Wafer from the production line! This shiny round disk is the pizza of the chip world?
Silicon Speech: (shaking his chopsticks) Wafer is the silicon-based “pizza crust”, from which thousands of Die can be cut—these are the unseasoned pizza slices!
Chip Language: (poking the wafer) So is a Chip the takeout pizza that packages the Die?
Silicon Speech: (nodding) You can be taught! But to transform a Die into a Chip, you first need to Bump— weld a few “teenage acne” on the Die, or use Wire Bonding to stitch with gold wire, or alternatively, use Flipchip to solder the Die upside down…
Chip Language: (raising a hand) I choose flip chip! Flipping it over can prevent kids from stealing the chips, right?
Silicon Speech: (rolling his eyes) Flip chip is to shorten the signal path! But does your design dare to pass the CP test?
Chip Language: (alert) CP? Is that a pre-debut assessment?
Silicon Speech: (tapping the bowl) CP (Chip Probing) is the “graduation exam” for chips on the wafer, using probes to test the functionality of the Die, those that fail get marked with an X! Only those that pass can be cut down, packaged into Chips, and sent for FT— the ultimate onboarding physical examination!
Chip Language: (holding his heart) So Yield is like me growing a field of strawberries, how many can I eat?
Silicon Speech: (serious) Insightful! But if the strawberries rot, it’s just sour; if the yield is below 80%, the boss will make you sour…
Jargon Science
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Wafer: A round disk made of silicon material, the “canvas” for chip manufacturing, commonly 12 inches in diameter (about the size of a pizza).
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Die: Independent chip units cut from the wafer, fragile like thin crackers before packaging.
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Chip: A packaged Die, wearing a “bulletproof vest” and able to connect to a circuit board.
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Bump: Tiny metal bumps on the Die used for connections during flip chip soldering.
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Wire Bonding: Connecting Die pins to the packaging substrate with gold or copper wire, akin to “chip embroidery”.
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Flipchip: Flipping the Die and connecting it directly to the substrate via bumps, offering better performance but at a higher cost.
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CP Testing: Testing to eliminate faulty Die before packaging, avoiding putting “bulletproof vests” on defective products.
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FT Testing: Comprehensive examination after packaging to ensure the chip can withstand real working environments.
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Yield: The proportion of qualified chips to total production, the lifeblood of semiconductor factories.
Follow Silicon Speech and Chip Language to unlock the classic jargon of the semiconductor industry!
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