Friends involved in IC design and verification know that simple single-core MCU code is everywhere. However, if you want to advance and study Multi-core Boot, Bus Arbitration, Cache Coherence, or Deadlock Detection, having a reliable multi-core RTL source code is essential. Without it, even the most skilled craftsman cannot cook without rice. At the end … Read more
In-Depth Analysis of Linux SMP Technology: From Principles to Practice 1 Basic Concepts of SMP Symmetric Multiprocessing (SMP) is a computer architecture technology that integrates multiple processors into a single system. Its core feature is that all processors work together in a peer-to-peer manner within a single operating system, sharing a unified memory space and … Read more
Table of Contents 1. Multi-level Cache of CPU 2. Improving Data Cache Hit Rate 3. Improving Instruction Cache Hit Rate 4. Improving Cache Hit Rate on Multi-core CPUs 5. Conclusion 🎉 Accumulating knowledge, sharing, and growing, so that both you and others can benefit! 😄 For more project courses, you can add me on WeChat … Read more
What is CoreMark? CoreMark is essentially a “tool” designed specifically for benchmarking embedded CPUs. Its goal is straightforward: to measure the computational power of the processor core without considering peripherals or operating systems, which are often seen as unnecessary distractions. Imagine you have a newly purchased MCU and want to know how fast it runs … Read more
The SG2042 uses the T-head Xuantie C910 core. It has a clock speed of 2.0GHz, with a total of 64 cores, where every 16 cores form a NUMA node, and there are 4 memory channels. The following tests were conducted using the vendor-provided GCC 10.2 version on an Ubuntu system with SSH remote access. In … Read more
1. Core Challenges of Real-Time Task Scheduling The real-time requirements of embedded systems dictate that tasks must be completed within strict time limits. This means that scheduling algorithms must consider not only the priority of tasks but also the deadline, execution time, and system resource utilization. Traditional scheduling algorithms such as Rate-Monotonic Scheduling (RMS) and … Read more
1. MOESI State Definitions The ARMv8 architecture uses the MOESI protocol to maintain data consistency across multiple cores. The MOESI protocol describes the state of a shared cache line in L1 Data Cache as follows: M, Modified, Unique Dirty, only exists in the current cache (unique) and the data in this cache line is different … Read more
Abstract Introduction (Overview of the Functional Characteristics and Market Applications of the S32K Series Automotive General-purpose MCU)1. Supported S32DS IDE Versions for S32K3xx MCU Software Development and Downloading and Installation2. Comparison of Debuggers Supporting S32K3xx MCU3. Compiling S32K3xx Multi-Core Projects Using S32DS v3.4 (Independent Compilation Settings and Multiple ELF vs. Single ELF) 3.1 Creating and … Read more
Table of Contents 1. Overview of SMP Architecture 1.1 Basic Concepts 1.2 FreeRTOS-SMP Features 2. Inter-Core Task Migration Experiment 2.1 Experiment Objectives 2.2 Experiment Steps 2.3 Experiment Result Analysis 3. Protection of Shared Resources in Multi-Core Systems 3.1 Common Issues 3.2 Comparison of Solutions 3.3 Example Code 4. Key API Analysis 4.1 SMP Extension APIs … Read more
In November 2023, the Hunan University Embedded and Network Computing Key Laboratory of Hunan Province’s Zephyr RTOS on RK3568 solution has been merged into the official Zephyr community, making it the first domestic solution (the second globally) to support multi-core ARMv8 architecture processor board patch, enabling support for the Firefly ROC-RK3568-PC development board, as shown … Read more