1. Overview of the Semiconductor Industry: The Ecological Chain from Design to Application The semiconductor industry chain exhibits a highly specialized structure, which can be divided into four major segments: Design: Companies like Qualcomm (mobile chips), NVIDIA (GPU), and Arm (IP licensing) are responsible for chip functionality architecture and circuit design. Manufacturing: Represented by TSMC and Samsung, this segment uses advanced processes (such as 3nm and 5nm) to “etch” design blueprints onto wafers, which is the segment with the highest technical barriers. Packaging and Testing: Companies like ASE and JCET are responsible for packaging bare chips into finished products and conducting functionality and reliability tests. Equipment and Materials: Companies such as Applied Materials (AMAT), ASML (lithography machines), and Tokyo Electron (etching machines) provide the core equipment and materials (such as photoresist and target materials) needed for manufacturing. In terms of market size, the global semiconductor market is expected to exceed $500 billion in 2023, and continues to grow driven by AI, autonomous driving, and the Internet of Things, with chips becoming the “industrial food” of the digital economy era. 2. The Complete Process of Chip Manufacturing: The Precise Journey from Silica Sand to Smart Chips 1. Silicon Wafer Preparation: The Transformation from “Grains of Sand” to “Wafers” Raw Material Purification: High-purity silicon is extracted from sand (silicon dioxide) and purified to “12 nines” (99.9999999999%) using the Siemens process, forming polycrystalline silicon granules. Monocrystalline Silicon Ingot Growth: Using the Czochralski (CZ) method, polycrystalline silicon is melted and pulled into a cylindrical monocrystalline silicon ingot (300mm diameter ingots can be up to 1.5 meters long, taking several days to grow). Wafer Slicing and Polishing: The ingot is sliced into thin silicon wafers using diamond saw blades, and then chemically mechanically polished (CMP) to achieve a surface flatness at the nanometer level, ensuring precision for subsequent processing. 2. Wafer Processing: The “Sculpting Art” of the Nanoworld (1) Epitaxial Growth (Epi): Building the Crystal “Foundation” A layer of epitaxial material, which is completely aligned with the underlying silicon crystal, is grown on the wafer surface through chemical vapor deposition (CVD). This layer can precisely control doping types (such as N-type and P-type) and thickness (from tens of nanometers to micrometers), providing a uniform crystal foundation for transistor manufacturing. (2) Photolithography: The Core Step of “Drawing Circuit Diagrams on Wafers” Coating: A photosensitive photoresist (positive/negative) is uniformly coated on the wafer surface through high-speed spinning (over 3000 RPM), with the thickness of the resist layer controllable to tens of nanometers.
Exposure: Traditional lithography uses deep ultraviolet light (DUV, wavelength 193nm) and employs “immersion lithography” (filling the space between the wafer and lens with water) to enhance resolution. Advanced lithography: Extreme ultraviolet lithography (EUV) is essential for processes at 7nm and below, utilizing 13.5nm wavelength extreme ultraviolet light, projecting patterns from masks onto wafers through multilayer mirrors (with precision reaching picometer levels), achieving line widths of several nanometers in a single exposure. Development and Etching: Chemical solutions dissolve the unexposed (or exposed) photoresist, revealing the underlying silicon layer; then, plasma etching (bombarding the silicon layer with charged particles) “copies” the photoresist pattern onto the silicon layer, forming a three-dimensional circuit structure. This “coating-exposure-etching” process must be repeated dozens of times, each time adding different circuit layers. (3) Transistor Manufacturing: The “Functional Cells” of Chips Transistors are the basic “switches” of chips, and their structural iterations drive leaps in chip performance: Planar MOSFET: An early structure where the gate is above the silicon surface, with increasing leakage current issues as processes shrink. FinFET (Fin Field-Effect Transistor): Silicon layers are etched into “fin shapes,” with gates wrapping around the fins from above, effectively controlling leakage current, becoming the mainstream structure for 14nm to 7nm processes. GAA (Gate-All-Around): The gate completely surrounds the silicon channel (such as Samsung’s 3nm MBCFET), further reducing power consumption and enhancing performance, representing the core direction for future advanced processes. During manufacturing, source and drain regions are formed by ion implantation (injecting boron, phosphorus, and other impurities into silicon to change conductivity type), and high-k dielectrics (such as HfO₂) + metal gates (such as TiN) replace traditional SiO₂ + poly-silicon gates to solve gate leakage issues. (4) Wiring: The “Nervous System” of Chips Transistors need to be connected into a complete circuit through metal wiring, with the process as follows: Metal Deposition: Physical vapor deposition (PVD) is used to deposit a copper seed layer, followed by electrochemical deposition (ECD) to fill copper, forming metal lines (copper’s conductivity is superior to traditional aluminum, reducing resistance). Multi-layer Interconnections and Vias: Through multiple lithography and etching steps, metal lines are formed at different layers, and inter-layer connections are achieved through vias. Advanced processes employ dual damascene techniques (simultaneously etching metal and dielectric layers, then filling with copper) to enhance wiring efficiency. Barrier Layers and Low-k Dielectrics: Barrier layers (such as TaN) are deposited around copper wiring to prevent copper diffusion, and low dielectric constant materials (such as porous SiO₂) are used for dielectric layers to reduce signal transmission delays. 3. Testing, Cutting, and Packaging: The “Last Mile” from Wafer to Finished Product Process Testing: Optical inspection (AOI) detects surface defects, electron beam inspection (EBI) checks internal circuit defects, and atomic force microscopy (AFM) measures critical dimensions to ensure precision at every step of the process. Wafer Cutting: Diamond dicing saws are used to cut wafers into individual bare chips (dies), with cutting precision controlled at the micrometer level to avoid damaging circuits.
Chip Packaging: Traditional Packaging: Bare chips are attached to lead frames, connected to pins through gold wire bonding, and then encapsulated in plastic. Advanced Packaging: Techniques such as CoWoS (Chip-on-Wafer-on-Substrate) enable multi-chip stacking, while Chiplet (chiplet) modularizes different functional chip integration, significantly enhancing integration and design flexibility. 3. Manufacturing Environment: The Ultimate “Dust-Free” Production Space Wafer manufacturing requires extremely high cleanliness standards, necessitating operation in a Class 1 cleanroom (where the number of particles ≥0.5μm per cubic foot of air is ≤1). Personnel must wear full cleanroom suits (bunny suits), and equipment is designed to be enclosed, even using wafer transfer robots (EFEM) for contactless wafer transport to minimize contamination. 4. Industry Challenges: Triple Pressure of Technology, Cost, and Geopolitics Technical Bottlenecks: Moore’s Law approaches physical limits, quantum tunneling effects lead to leakage, and lithography resolution nears the diffraction limit of light; simultaneously, process scaling increases design complexity and manufacturing costs exponentially (investments in 3nm fabs exceed $5 billion). Supply Chain Fragmentation: Geopolitical factors lead to export restrictions on equipment and materials (such as EUV lithography machines and high-end photoresists), necessitating a restructuring of the global semiconductor supply chain. Energy Consumption and Yield: Advanced process chip manufacturing has extremely high energy consumption, and improving yield is challenging (for example, initial yields for 5nm were below 50%), further driving up costs. 5. Future Trends: Technological Innovations Open New Avenues 3D Packaging and Chiplets: By vertically stacking and integrating chiplets, limitations of planar processes are overcome, achieving “heterogeneous integration” (such as the multi-die integration in Apple’s M series chips). New Materials and Structures: Exploring two-dimensional materials (such as graphene and MoS₂) to replace silicon, and new structures like GAA and Forksheet transistors to enhance performance. AI and Smart Manufacturing: Utilizing machine learning to optimize process parameters (such as lithography focus and etching rates), achieving yield prediction and real-time control, reducing manufacturing costs. Green Manufacturing: Developing low-power devices and recycling process chemicals to reduce the environmental footprint of chip manufacturing. The manufacturing of semiconductor chips represents the pinnacle of human industrial civilization, with each breakthrough in processing embodying the wisdom of multiple disciplines including materials, physics, mechanics, and electronics. Amidst the intertwining of technical bottlenecks and industrial transformation, its future will not only concern the chips themselves but will profoundly impact the development pattern of the global digital economy.