Zhongke Benyuan is set to launch the FDM-RV0025 DSP, based on the next-generation RISC-V architecture core SummerCoreTM, which is optimized for applications in industrial control, servo motors, inverters, and converters. Compared to foreign benchmark products, it shows significant improvements in clock frequency, memory capacity, algorithm performance, signal chain processing speed, and interface transmission rates.
Introduction to the RISC-V Architecture SummerCoreTM
Figure 1: Structural Block Diagram of the RISC-V Architecture SummerCore
SummerCoreTM is a second-generation RISC-V architecture DSP core independently developed by Benyuan. Based on 150 standard RISC-V instructions, it expands 242 custom instructions aimed at algorithms in industrial control, new energy, and humanoid robots, adding hardware modules such as trigonometric function calculation units and fast integer division units to efficiently support these instructions, significantly enhancing the computational performance of SummerCoreTM in digital signal processing.
Typical Specifications of FDM-RV0025
| Product | FDM-RV0025 | Foreign Benchmark Product |
| Clock Frequency | 150MHz | 100MHz |
| Peak Computing Power | 600MIPS | 100MIPS |
| Peak Floating Point Performance | 150MIPS | 100MIPS |
| On-chip Memory | 256KB (64KW) Flash48KB (12KW) RAM | 128KB (64KW) Flash24KB (12KW) RAM |
| CAN | 1 | 1 |
| CAN-FD | 1 | Not Supported |
| ADC | 2 at 3.45MSPS, 12-bit | 2 at 3.45MSPS, 12-bit |
| PWM | 14 ePWM (8 HRPWM) | 14 ePWM (8 HRPWM) |
| eCAP | 3 eCAP (1 HRCAP) | 3 eCAP (1 HRCAP) |
| eQEP | 2 supporting CW/CCW operation modes | 2 supporting CW/CCW operation modes |
| CMPSS | 4 with 12-bit DAC | 4 with 12-bit DAC |
| CLB | 1 | 1 |
| LIN | 2 | 2 |
| DMA | 6 Channels | 6 Channels |
Table 1: Comparison of Typical Specification Parameters
Typical Algorithm Performance of FDM-RV0025
FOC (Field-Oriented Control) is a high-performance motor control technology that achieves independent and precise control of motor flux and torque by decomposing the three-phase motor’s stator current into excitation and torque components. Its applications are widespread, covering various fields such as industry and transportation, especially suitable for scenarios with high demands on motor dynamic response, speed range, and control accuracy.
Figure 2: FOC Current Loop Implementation Block Diagram
The current loop calculation of the FOC algorithm (as shown above) has high computational performance requirements, which directly determines the system’s real-time processing capability. The RV0025 DSP chip operates at a clock frequency of 150MHz, requiring 179 cycles for current loop calculations, with an execution time of approximately 1.2us, which is about half the execution time of international benchmark products (which operate at 100MHz and have a current loop execution time of approximately 2.39us).
| Function | RV Cycle Count |
| CLARKE | 13 |
| PARK | 20 |
| PI_Q | 30 |
| PI_D | 30 |
| IPARK24 | |
| SVGENDQ | 35 |
| PWM | 27 |
| Total | 179 |
Table 2: FOC Current Loop Performance Data
FDM-RV0025 Signal Chain Performance
The signal chain refers to a series of components or modules in an electronic system used for sensing, converting, processing, transmitting, and outputting signals, including interrupt handling, ADC sampling conversion, DSP core computation, and PWM control processes. It is widely used in various electronic systems that require signal acquisition, processing, and transmission, covering industrial, electronic, and communication fields, and is an important indicator of DSP real-time processing capability.
Figure 3: Signal Chain Data Flow Block Diagram
The RV0025 DSP chip integrates high-performance analog modules and is tightly coupled with the DSP core and PWM units, providing low latency for signal processing, transmission, and response, thus offering better signal chain performance. The RV0025 DSP chip requires 523 cycles for signal chain processing, with an execution time of approximately 3.5us at a clock frequency of 150MHz, which is more than a 50% reduction in execution time compared to international benchmark products (which operate at 100MHz and have an execution time of 7.8us).
| Test Item | RV Cycle Count |
| Interrupt Latency | 8 |
| ADC Sample | 4 |
| Clarke Transformation | 13 |
| Clarke Inverse Transformation | 14 |
| PID Controller Transformation | 99 |
| Park Transformation | 20 |
| Park Inverse Transformation | 24 |
| SVGen Transformation | 54 |
| Speed Estimation | 51 |
| Flux Estimation | 105 |
| ACI | 121 |
| PWM | 10 |
| Total | 523 |
Table 3: Signal Chain Performance Data
From the above data comparison, it is evident that the FDM-RV0025 is a high-performance DSP chip based on the RISC-V architecture, fully innovated and developed independently. Compared to foreign benchmark products, it shows significant improvements in operating frequency, algorithm performance, and can better meet the demands for high-performance real-time processing processors in industrial control, new energy, and humanoid robot fields.
Guided by: Zhang Zhiwei Edited by: Xing Yuanyuan, Gao Yuxin
Reviewed by: Xiao Ruozhou
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