Friends, let’s talk about the recent hot topic in the semiconductor circle—advanced packaging. In this era of constant innovation in the industry, it has become increasingly difficult to enhance performance solely by reducing chip size due to physical limitations. At this moment, advanced packaging technology emerges as a refreshing stream, taking center stage and becoming a strategic high ground that major wafer manufacturers are eager to occupy. Why? Because it allows for tighter integration of chips without altering the chip manufacturing process, making them smaller while also reducing costs, perfectly aligning with the high-end chip trend of pursuing “small, fast, and economical,” and is essentially the key to continuing or even surpassing Moore’s Law. In recent years, in addition to the familiar CoWoS, new faces like CoPoS and EMIB-T have also made their debut, with major manufacturers gearing up for a new round of technological land grab in this new battlefield of advanced packaging.
Taiwan Semiconductor Manufacturing Company (TSMC): From “Crooked Neck Tree” to “Towering Tree”?
Speaking of TSMC, it is a perennial champion in the semiconductor manufacturing field. They have also been active in advanced packaging, launching a new technology called CoPoS (Chip-on-Package-on-Substrate), with the slogan “Transforming Round into Square.” What does this mean? Traditional packaging resembles a “crooked neck tree,” where the wafer is round and the packaging substrate is square, leading to some inherent disharmony. CoPoS directly arranges the chips on a large square board, effectively straightening the “trunk,” representing a significant upgrade to the existing CoWoS technology. Specifically, it changes the traditional round wafer into a 310×310 mm square, significantly increasing area utilization, estimated to save 15%-20% in costs, which is quite appealing. TSMC is not stopping there; they have already planned a mass production line for CoPoS at the Chiayi AP7 plant, aiming for launch between the end of 2028 and 2029. This AP7 plant is a “giant,” built in several phases, specifically reserving P4 for CoPoS, P2/P3 for SoIC technology, and a dedicated spot for Apple’s WMCM (wafer-level multi-chip module). Compared to the older packaging base, the Nanke AP8, AP7 has more space and better facilities, likely becoming TSMC’s “base camp” for integrating various cutting-edge packaging technologies. It is rumored that TSMC is already preparing for trial production of WMCM for Apple’s A20 chip in 2026, a technology that can integrate multiple chips at the wafer stage, resulting in a smaller size and faster signals, which sounds advanced.
Intel: EMIB Evolves Again, TSV Bridges the Gap
Intel has also been a veteran player in the packaging field, with their EMIB (Embedded Multi-die Interconnect Bridge) technology already in widespread use, breaking through photomask limitations to enable high-speed “communication” between multiple chips. Simply put, it involves embedding a small silicon chip in areas requiring high-density connections to act as a “bridge,” while other areas continue to use traditional methods. Now, Intel has upgraded to EMIB-T, with the key enhancement being the addition of Through-Silicon Via (TSV) technology. Previously, chip power was supplied via “cantilevers,” but now a TSV “hole” is created at the bottom for direct power supply, reducing resistance and increasing efficiency, particularly suitable for feeding high-performance memory like HBM4. TSV also significantly increases the communication bandwidth between chips, easily exceeding 32 Gb/s, and is compatible with the latest UCIe-A standard. To prevent signal interference, Intel has added a “capacitor shield” in the bridge to ensure stable signals. At a recent technology conference, Intel not only showcased the power supply advantages of EMIB-T but also revealed plans to improve yield rates for large-size packaging using Thermal Compression Bonding (TCB) technology and to develop new cooling solutions to address chip heating challenges. After all, the more complex the chip, the more it acts like a “small furnace,” making heat dissipation a significant issue.
UMC: The Veteran Player Also Wants to Master 3D
UMC, as a “big brother” in the wafer foundry industry, has not fallen behind in advanced packaging and has been making frequent moves recently. There are rumors that UMC plans to acquire a factory in Nanke to vigorously develop advanced packaging. Although UMC has not officially responded, senior management has indicated that advanced packaging will be a key focus in their future capacity planning in Taiwan. UMC has an advantage: they have already established a 2.5D packaging line in Singapore and possess wafer-to-wafer bonding (W2W) technology, which is a “nuclear weapon” in 3D ICs. The Fab 12A plant in Taiwan has also mastered 14nm technology for high-end customization. In the future, UMC plans to combine these technologies to launch a more comprehensive advanced packaging solution in Taiwan. Their CEO, Liu Qidong, has stated that UMC will not only engage in traditional foundry work but will also cross into the high-value-added advanced packaging field. They are not only producing 2.5D interposers but are also developing WoW hybrid bonding technology, having secured a major packaging contract for Qualcomm’s HPC products, which are relevant to the AI PC, automotive, and AI server markets, and may even be used in HBM integration. This move breaks the “tripod” situation of TSMC, Intel, and Samsung. UMC has stated that advanced packaging is a key direction and will collaborate with subsidiaries like ZhiYuan and XiTong, as well as partners like Winbond, to build their own packaging “circle of friends.”
Samsung: SAINT Technology Stacks Up
Samsung is naturally not willing to be outdone and has unveiled its own SAINT (Samsung Advanced Interconnect Technology). This system includes three types of 3D stacking technologies: SAINT-S (for SRAM), SAINT-L (for logic chips), and SAINT-D (stacking DRAM on logic chips, such as HBM stacked on CPU/GPU). Samsung’s approach is quite unique; instead of using a silicon interposer to connect HBM and GPU as in traditional 2.5D, they directly stack HBM chips vertically on the processor, like building blocks. This saves the silicon interposer but makes the process more complex, requiring the creation of new substrates. To support this operation, Samsung is actively expanding production domestically and collaborating with local governments to plan the construction of an advanced HBM packaging plant in Tianjin, Korea, scheduled for completion in 2027. Additionally, they have established a packaging laboratory (APL) in Yokohama, Japan, dedicated to researching the next generation of packaging, targeting clients in HBM, AI, and 5G markets.
AI and HBM: The “Golden Partners” of Advanced Packaging
Observant friends may have noticed that whether it is TSMC, Intel, or Samsung, their advanced packaging solutions are closely related to HBM (High Bandwidth Memory). Why? Because AI is booming! Applications like deep learning, big data, and natural language processing require processing massive amounts of data, with high demands on memory speed and bandwidth. HBM is like the “high-speed train” of memory, with lightning-fast speeds. Advanced packaging technology allows HBM chips and processor chips to be more tightly integrated, enabling faster data transmission, thereby enhancing overall system performance and energy efficiency. Currently, the packaging method for HBM4 is also changing, shifting from horizontal “hand-holding” (2.5D) to vertical “stacking” (3D). Major manufacturers are all focusing on HBM, with TSMC’s CoWoS/CoPoS, Intel’s EMIB-T, and Samsung’s SAINT all making efforts in this area. The enormous demand from the AI market acts like an invisible hand, pushing major wafer manufacturers to continuously innovate in advanced packaging, all aiming to seize the high ground in the semiconductor market in this new era.
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