1. Hardware Floating-Point and Software Floating-Point
In ARMv8, hardware floating-point is part of the architecture.AArch32 state supports software floating-point, but AArch64 state does not support software floating-point.
ARM systems may have:
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A VFP coprocessor, which supports hardware floating-point.
- No floating-point hardware, meaning does not support hardware floating-point.
If you compile for a system with a hardware VFP coprocessor, the ARM compiler will use it. If you compile for a system without a coprocessor, the compiler will implement calculations in software. For example, the compiler option<span>-mfloat-abi=hard</span> selects the hardware VFP coprocessor, while the option<span>-mfloat-abi=soft</span> specifies that arithmetic operations will be performed in software without using any coprocessor instructions.
2. Introduction to Floating-Point Types in ARMv8
The floating-point register set uses the same extended registers as the SIMD registers and is banked. In AArch32 state, the floating-point support has not changed significantly from VFPv4, except for the addition of some instructions compliant with the IEEE 754 standard.
The floating-point architecture in AArch64 state is also based on VFPv4.The main differences are as follows:
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In AArch64 state, the number of 128-bit SIMD and floating-point registers increases from 16 to 32.
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Single-precision registers are no longer packed into double-precision registers, so register Sx is D x[31:0].
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The presence of floating-point hardware is mandatory, so software floating-point linking is not supported.
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AArch64 state does not support earlier versions of the floating-point architecture, such as VFPv2, VFPv3, and VFPv4.
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Neither AArch32 nor AArch64 state supports VFP vector mode. Use advanced SIMD instructions for vector floating-point.
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Some new instructions have been added, including direct conversions between half-precision and double-precision, loading and storing pairs, replacing multiple loads and stores, fused multiply-add and multiply-subtract, and IEEE 754-2008 compatibility instructions.
3. Map of Extended Registers
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32 128-bit registers V0-V31. (also called q0-q31, which are directly mapped to v0-v31)
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32 64-bit registers D0-D31.
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32 32-bit registers S0-S31.
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32 16-bit registers H0-H31.
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32 8-bit registers B0-B31.
4. Store Instructions for Floating-Point Registers
For example:
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LDP Qt1, Qt2, addr // Load two consecutive words from memory addressed by addr into 128-bit Qt1 and Qt2.
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STP Qt1, Qt2, addr // Store the two consecutive words of 128-bit Qt1 and Qt2 into memory addressed by addr.
(Usage example)
5. Comparison between SIMD and Floating-Point Types
Basic Concepts:
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VFP: Refers to the architecture of floating-point units, such as vfpv3 and vfpv4, with vfpv4 currently used in armv8.
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FP: Refers to hardware floating-point instructions.
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SIMD: Refers to SIMD instructions.
- NEON: A technology that provides SIMD instructions.
Supplementary Introduction to NEON
NEON: Arm Neon technology is an advanced single instruction multiple data (SIMD) architecture extension suitable for Arm Cortex-A and Cortex-R series processors. Neon technology aims to enhance multimedia user experience by accelerating audio and video encoding and decoding, user interfaces, 2D/3D graphics, and gaming. Neon can also accelerate signal processing algorithms and functionalities to speed up applications such as audio and video processing, speech and facial recognition, computer vision, and deep learning.
As a software engineer, you can utilize ARM NEON technology in the following ways:
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Neon intrinsics
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Neon-enabled libraries
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Auto-vectorization by your compiler
- Hand-coded Neon assembler
Summary: Personal insights. VFP is a unit (similar to an ALU) that operates on v0-v31 registers (also referred to as q0-q31) to perform floating-point operations. The NEON technology also provides some SIMD instructions, using the VFP unit and the V0-V31 registers.