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First, let’s look at a block diagram. After an interrupt occurs, the PC will jump to VBAR + interrupt offset. For example, the blue part in the diagram 
There are three base addresses: VBAR_EL1, VBAR_EL3, and VBAR_EL1 (secure). Which one should be used? This is determined by the table titled Routing when both EL3 and EL2 are implemented. If the interrupt routing goes to EL1, VBAR_EL1 is used; if it routes to EL3, VBAR_EL3 is used; if it routes to secure EL1, VBAR_EL1 (secure) is used.
After selecting the base address, how do we choose the offset? We see that the vector table has four rows; which row should be chosen? This is determined by the table titled Vector offsets from vector table base address 
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If an exception occurs but does not cause an exception level switch, and the stack pointer used is SP_EL0, then the first group of exception vector tables is used.
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If an exception occurs but does not cause an exception level switch, and the stack pointer used is SP_EL1/2/3, then the second group of exception vector tables is used.
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If an exception occurs that causes an exception level switch, and the lower exception level is running in AARCH64 mode, then the third group of exception vector tables is used.
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If an exception occurs that causes an exception level switch, and the lower exception level is running in AARCH32 mode, then the fourth group of exception vector tables is used.
After selecting a specific row from the interrupt vector table, how do we choose which offset? This will be determined by the type of interrupt. If it is IRQ or FIQ, it will depend on the current PE state and interrupt configuration attributes to decide between IRQ or FIQ 
The mask for interrupts is determined by the table below (Physical interrupt target and masking when both EL3 and EL2 are implemented)


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