The Memory Systems defined by ARMv8-A mainly unfold from three parts: Memory types, Memory attributes, and Barriers, which are introduced one by one below.
1. Memory types
The ARMv8-A architecture defines two mutually exclusive memory types: Normal and Device. All memory regions are configured as one of these two types.
1.1 Normal memory
Normal memory is used for all code and most data areas in memory, such as RAM, Flash, or ROM regions in physical memory. This type of memory provides the highest processor performance because it is weakly ordered, allowing the compiler to perform more optimizations. The processor can reorder, repeat, and merge accesses to normal memory.
The processor can speculatively access addresses marked as Normal, allowing data or instructions to be read from memory without explicit references in the program or before the actual execution of explicit references. This speculative access may occur due to branch prediction, speculative cache line filling, out-of-order data loading, or other hardware optimizations.
1.2 Device memory
The Device memory type is used for memory-mapped peripherals and all memory areas where accesses may have side effects. For example, reading from a timer is non-repeatable because the return value differs each time. Writing to control registers can trigger interrupts. The Device memory type imposes more restrictions on the kernel.
There are four different types of device memory, defining the rules that memory access must comply with:
• Device-nGnRnE is the most restrictive.
• Device-nGnRE
• Device-nGRE
• Device-GRE is the least restrictive.
1) Gathering or non-Gathering
Gathering or non-Gathering (G or nG) determines whether multiple accesses to the memory region can be combined into a single transaction. If the address is marked as non-Gathering (nG), then the number and size of accesses to that address must exactly match the number and size explicitly accessed in the code. If the address is marked as Gathering (G), then the processor can combine two byte writes into a half-word write.
2) Reordering
Reordering (R or NR) determines whether accesses to the same device can be reordered relative to other accesses. If the address is marked as non-reordering (NR), then accesses to the same block of memory always appear on the bus in program order.
3) Early Write Acknowledgment
Early Write Acknowledgment (E or nE) determines whether the intermediate write buffer between the processor and the accessed device is allowed to send a write complete acknowledgment. If the address is marked as non-early write acknowledgment (nE), then the write response must come from the peripheral. If the address is marked as early write acknowledgment (E), then it is a buffer in the interconnect logic that can issue a write accepted signal before the write is actually received by the terminal device.
The following diagram shows the four different types of device memory:
2. Memory attributes
The system’s memory mapping can be divided into several regions. Each region can have different memory attributes, such as access permissions (including read and write permissions at different privilege levels), memory types, cache policies, etc.
The following diagram is an example of system memory mapping:
Code and data functional fragments are grouped in the memory mapping, with each region’s attributes controlled by the MMU.
In addition to memory types, memory attributes also provide control over cacheability, shareability, access, and execution permissions. Shareable and cache properties only apply to Normal memory. Device regions are always Non-cacheable and Outer-shareable.
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Cacheable
Memory regions marked as “Normal” can be specified as cached or non-cached, and memory cache properties can be controlled through internal and external attributes for multi-level caches.
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Shareable
The shareable attribute is used to define whether a location is shared among multiple cores. Marking a region as Non-shareable means it is only used by a specific core, while marking it as Inner Shareable or Outer Shareable, or both, means that the location is shared with other observers (e.g., GPU or DMA).
2.1 Domains
Data memory access may take longer and consume more power compared to using cache coherency hardware. This overhead can be minimized by maintaining consistency among a smaller number of main servers, ensuring they are physically close within the processor. For this reason, the architecture divides the system into multiple Domains, making it possible to limit overhead to those locations that require consistency.
The following diagram shows the shareability domain options:
The following table lists the available shareability domain options:
3. Barriers
The Arm architecture includes Barriers instructions that enforce access ordering and completion at specific points.
Barriers are used to prevent unsafe optimizations and enforce specific memory order. Therefore, using unnecessary Barrier instructions can degrade software performance. Carefully consider whether a Barrier is needed in specific cases, and if so, which type of Barrier is appropriate.
The following introduces three types of Barrier instructions:
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Instruction Synchronization Barrier
Instruction Synchronization Barrier (ISB) is used to ensure the fetching of any subsequent instructions, allowing the current MMU configuration to check privileges and access. It is used to ensure that any previously executed context change operations (e.g., writing to system control registers) are completed by the time the ISB is finished.
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Data Memory Barrier
Data Memory Barrier (DMB) prevents the reordering of data access instructions across the DMB instruction.
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Data Synchronization Barrier
Data Synchronization Barrier (DSB) enforces the same ordering as the Data Memory Barrier, but it also prevents the execution of any further instructions, not just loads or stores, until synchronization is complete.
DMB and DSB instructions accept a parameter that specifies the type of access before or after the barrier operation, as well as the shareability domain to which it applies.
The following table lists the available parameter options:
Synchronization Group:
