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Continuing from the previous article on ARMV8-A MMU – Part 1.
IPS[34:32] (Intermediate Physical Address Size) controls the size of the IPA address space. When IPS=000, it indicates a 32-bit address space; when IPS=101, it indicates a 48-bit address space. The meanings of other values can be referenced in the ARMv8 documentation.
After setting the address space size, if subsequent software accesses exceed this address range, an access error will be triggered. Let’s review the TCR_EL1 register [31:0], as shown in Figure 3.
TG1[31:30] and TG0[15:14] control the page size described by the page tables for kernel and user mode. When the two bits are set to 00, it indicates a page size of 4K; when set to 01, it indicates a page size of 16K; when set to 11, it indicates a page size of 64K. These values indicate that when the MMU maps virtual addresses to physical addresses, the smallest mapping units are 4K, 16K, and 64K.
We can configure the number of page table levels for the first lookup in the page table. In a 64-bit ARMv8 system, the maximum number of page table levels is 4. We do not have to implement all 4 levels; we can configure different page table levels based on actual conditions. The first-level page table is controlled by the TG and TxSZ bits in TCR_EL1, and can control the page table granularity and number of levels for TTBR0_EL1 and TTBR1_EL1 separately.
How does TxSZ specifically affect the size of the virtual address space? According to the official ARMv8 manual, the calculation method for the virtual address space is:2(64-T1SZ) exponent. The range of TxSZ values is: 0~2(5). Therefore, the maximum value of the virtual address space size is:2(64-63)~2(64-0), which is, 2~2(64).
Virtual Address to Physical Address Translation
When the processor accesses a virtual address, such as fetching instructions or reading/writing data, the MMU will convert that virtual address into a physical address.
For example, in a virtual address translation process using a single-level page table, let’s assume the page table’s page granularity is 64K, and the virtual address space size is 42 bits. The MMU performs the virtual address to physical address translation as follows:
Step 1: If the virtual address VA[63:42]= all 1s, the MMU will choose TTBR1_EL1 as the base address for the page table; if the virtual address VA[63:42]= all 0s, the MMU will choose TTBR0_EL1 as the base address for the page table;
Step 2: The page table base address contains 8192 x 64-bit page table entry entries, which are indexed using VA[41:29]. The MMU then reads the related next-level translation table entry from the table.
Step 3: The MMU checks the validity of the translation table entry and determines whether the requested virtual address has the correct access permissions. If the check passes, access to that memory address is allowed.
Step 4: In Figure 4 below, the MMU is dissected for addressing the virtual address, where each entry in the translation table is associated with a 512MB huge page (also called a block descriptor). The virtual address VA[47:29] will be passed along as part of the physical address addressing, as bits of the physical address PA[47:29].
It is worth noting that: because it supports a maximum of 8192 entries, the MMU does not use the [48:43] bits of the virtual address. However, these bits are needed when looking up the physical address.
Step 5: The virtual address VA[28:0] will also be passed along as part of the physical address addressing, as bits of the physical address PA[28:0].
The final physical address, a full 48-bit address, will be found and returned by the MMU. This is just a simple example of virtual address to physical address translation. If this example were applied in real scenarios, this translation process would severely limit the fine division of the address space. Therefore, it is not recommended to use this method for the MMU to establish page tables.
Unlike the simple single-level page table conversion example above, in actual scenarios, the operating system will use multi-level page tables for more refined division, reducing the page granularity, for example, from a 512M huge page to a more conventional 4K page size.
We welcome everyone to continue reading the next article “Introduction to ARMV8-A MMU – Part 3”.
