Understanding ARMv8-A Architecture

In previous articles, we often mentioned Armv8-A. So what exactly is Armv8-A? This question can be simple or complex. Today, let’s take some time to briefly study it.

As we all know, ARM is a company that designs and licenses processors and corresponding IPs (such as interconnect buses, interrupt controllers, image processors, etc.). Currently, its processor products are divided into three categories:

• Cortex-A Series: This series primarily consists of application processors. These processors are characterized by high performance, generally supporting technologies such as cache, out-of-order execution, branch prediction, and multiple instruction issuing.
• Cortex-R Series: This series mainly consists of real-time processors. These processors are characterized by a controllable response time to external events. Here, real-time does not mean the processor is fast, but rather that the response time to external events is predictable.

• Cortex-M Series: This series mainly consists of microcontroller processors. These processors are generally designed to be relatively simple, with small chip sizes and low power consumption, typically used as controllers for low-cost chips.

The representative letters of these three series add up to ARM, which should be intentional by ARM. In fact, ARM’s processor products were not named this way a long time ago, such as the earlier ARM9 and ARM11. Now ARM’s processor products have also added the Neoverse series, distinguishing it from the A series processors, but that’s a topic for later; for now, let’s just consider the three series.

Returning to Armv8.x-A, the prefix Arm needs no explanation; v indicates the version; 8 is the major version number; x represents the extension version number, also known as the minor version number. For example, 8.4 indicates that the major version is 8 and the extension version is 4, with the base version of Armv8-A being Armv8.0-A. The final A indicates the A series, so there should also be R and M, right? However, I have little knowledge of R and M, so I will not introduce them; the following content will be based on A.

Armv8-A has two execution states: AArch64 and AArch32. Correspondingly, Armv8-A supports two instruction sets: AArch64 (A64) and AArch32, with AArch32 further divided into A32 and T32. A64 is a fixed-length instruction set with 32-bit instruction encoding; A32 is also a fixed-length instruction set with 32-bit instruction encoding; T32 is a variable-length instruction set with 16-bit and 32-bit instruction encoding. Since A32 and T32 are mainly for forward compatibility, they are rarely used in Armv8-A; the following content will mainly introduce AArch64-related topics.

AArch64 has extended some registers, including the following: 31 general 64-bit registers (X0-X30), the processor state register PSTATE, and several related registers, stack register SP, etc. I will find time to analyze these registers in detail later.

Armv8-A defines four exception levels (Exception Levels), which have been repeated many times in previous articles.

Armv8-A supports GICv3, GICv4, SMMU3.

For the specific implementation of the instruction set of its processors, ARM has a convention. For instance, if a processor implements Armv8.1-A, then that processor:

• Must implement the mandatory functions required by Armv8.0-A and Armv8.1-A.
• May implement certain extended functions from Armv8.2-A.

• Is not allowed to implement extended functions from Armv8.3-A and higher versions.

Regarding the functions required by Armv8.0-A, I will analyze them gradually when I have the opportunity. This is not something that can be completed overnight, as the architecture documentation alone exceeds ten thousand pages. For now, I will simply list the extended functions of versions after Armv8.0-A, and later we will analyze the basic functions of Armv8.0-A and these extended functions.

1. Armv8.1-A

• Atomic memory access instructions (AArch64)
• Limited Order regions (AArch64)
• Increased Virtual Machine Identifier (VMID) size, and Virtualization Host Extensions (AArch64)
• Privileged Access Never (PAN) (AArch32 and AArch64)

2. Armv8.2-A

• Support for 52-bit addresses (AArch64)
• The ability for PEs to share Translation Lookaside Buffer (TLB) entries (AArch32 and AArch64)
• FP16 data processing instructions (AArch32 and AArch64)
• Statistical profiling (AArch64)

• Reliability Availability Serviceability (RAS) support becomes mandatory (AArch32 and AArch64)

3. Armv8.3-A

• Pointer authentication (AArch64)
• Nested virtualization (AArch64)
• Advanced Single Instruction Multiple Data (SIMD) complex number support (AArch32 and AArch64)
• Improved JavaScript data type conversion support (AArch32 and AArch64)
• A change to the memory consistency model (AArch64)

• ID mechanism support for larger system-visible caches (AArch32 and AArch64)

4. Armv8.4-A

• Secure virtualization (AArch64)
• Nested virtualization enhancements (AArch64)
• Small translation table support (AArch64)
• Relaxed alignment restrictions (AArch32 and AArch64)
• Memory Partitioning and Monitoring (MPAM) (AArch32 and AArch64)
• Additional crypto support (AArch32 and AArch64)
• Generic counter scaling (AArch32 and AArch64)

• Instructions to accelerate SHA

5. Armv8.5-A and Armv9.0-A

• Memory Tagging (AArch64)
• Branch Target Identification (AArch64)
• Random Number Generator instructions (AArch64)

• Cache Clean to Point of Deep Persistence (AArch64)

6. Armv8.6-A and Armv9.1-A

• General Matrix Multiply (GEMM) instructions (AArch64)
• Fine grained traps for virtualization (AArch64)
• High precision Generic Timer

• Data Gathering Hint (AArch64)

7. Armv8.7-A and Armv9.2-A

• Enhanced support for PCIe hot plug (AArch64)
• Atomic 64-byte load and stores to accelerators (AArch64)
• Wait For Instruction (WFI) and Wait For Event (WFE) with timeout (AArch64)

• Branch-Record recording (Armv9.2 only)

5.8 Armv8.8-A and Armv9.3-A

• Non-maskable interrupts (AArch64)
• Instructions to optimize memcpy() and memset() style operations (AArch64)
• Enhancements to PAC (AArch64)

• Hinted conditional branches

Armv9-A is the latest architecture from ARM, but it has not yet been fully disclosed.

Lastly, it is worth mentioning that the design of multi-core server chips based on ARM processors is booming, with more and more players emerging both domestically and internationally. ARM has introduced the Server Base System Architecture (SBSA) specification, which outlines the hardware requirements for servers. The table below summarizes the SBSA requirements related to Armv8.x-A.

The SBSA document is publicly available, and interested friends can download it from the official website. The version of the SBSA document I currently see is 7.0, released in January 2021.

Actually, the SBSA specifies some rules, with different requirements for different levels. The following diagram shows the requirements for processors, SMMU, and GIC at different levels of SBSA, which can be viewed in conjunction with the previous image.

Finally, I have mustered the courage to start tackling the ARM architecture manual. With over ten thousand pages of documentation, we will take it slow, making a little progress each day.

Wishing everyone a pleasant weekend!