In ARMv8, memory is divided into two types:Normal memory and Device memory, where Normal memory is suitable for most of the memory in the system, while Device memory is used for memory utilized by peripherals.
1. Normal Memory
The Normal memory type attributes apply to most memory in the system. It indicates that the architecture allows hardware to perform speculative data read accesses to these locations, regardless of the access permissions of these locations. To ensure the ordering of accesses to Normal memory, it is necessary to use memory barrier instructions: DMB.
1.1 Shareable Normal Memory
A Normal memory address can have one of the following Shareability attributes:
Inner Shareable, applicable to Inner Shareable shareability regions.
Outer Shareable, applicable to Inner Shareable and Outer Shareable shareability regions.
Non-shareable.
1.1.1 Inner Shareable and Outer Shareable Attributes
The ARM architecture abstracts the system into a series of Inner and Outer shareable attribute regions.
Each Inner shareable domain contains a set of observers, which are data consistent for each member of that group, used for data access with the Inner Shareable attribute created by any member of that group.
Each Outer shareable domain contains a set of observers, which are data consistent for each member of that group, used for data access with the Outer Shareable attribute created by any member of that group.
It also possesses the following properties:
Each observer is merely a member of an inner shareable domain.
Each observer can only be a member of a single outer shareable domain.
All observers in an inner shareable domain are always members of the same outer shareable domain.
This means that the inner shareable domain is a subset of the outer shareable domain, although it does not need to be a proper subset.
Since all data accesses to non-cacheable locations are data consistent for all observers, non-cacheable locations are always viewed as Outer Shareable. The inner shareable domain is expected to be a collection of PEs controlled by a single hypervisor or operating system.
If there are two processor clusters in a system, it must be ensured that:
Within each cluster, the data caches and unified caches of the processors are transparent to all data accesses to memory locations with the Inner Shareable attribute.
However, between the two clusters, if only the Inner Shareable attribute is present, caches do not need to maintain consistency in data accesses. If the Outer Shareable attribute is present, data consistency is required.
In such a system, for the Inner Shareable attribute, each cluster is in a different shareability region, but for the Outer Shareable attribute, all components in the subsystem are in the same shareability region.
A system may implement two such subsystems; if the data cache and unified cache of one subsystem are opaque to accesses from other subsystems, then the system has two Outer shareable regions.
For shareable Normal memory, Load-Exclusive and Store-Exclusive instructions consider the possibility of multiple observers (multiple cores) accessing the same shared domain.
1.2 Non-shareable Normal Memory
For Normal memory regions, non-shareable normal memory is a block of Normal memory that can only be accessed by a single CPU. Non-shareable Normal memory does not require hardware to guarantee consistency of data accesses among multiple observers unless the memory is non-cacheable.
For non-shareable memory, if other observers share this memory system, software must use cache maintenance instructions to ensure cache consistency issues in data communication among multiple observers. Additionally, extra memory barrier operations are needed to ensure the order of memory processing.
Moreover, for non-shareable memory, whether Load-Exclusive and Store-Exclusive instructions consider the possibility of multiple observers accessing it is IMPLEMENTATION DEFINED.
1.3 Cacheability Attributes for Normal Memory
In addition to the Outer Shareable, Inner Shareable, and Non-shareable attributes, each Normal memory is also assigned a cache attribute:
Write-Through Cacheable.Write-Back Cacheable.
Non-cacheable.
The cache attributes provide a consistency control mechanism for observers located outside the memory area shareable domain. In some cases, using Write-Through cache or non-cacheable regions may offer a better mechanism for controlling consistency compared to using hardware consistency mechanisms or cache maintenance programs. To this end, the architecture requires non-cacheable or Write-Through cache memory to have the following properties:
When an observer accesses memory systems within a certain level of cache, complete writes to the Write-Through cache or non-cacheable memory locations at that level of cache are visible to all observers accessing memory systems outside that level of cache without requiring explicit cache maintenance.
Writes to non-cacheable memory locations at that level of cache, completed by observers accessing memory systems outside that level of cache, are visible to all observers accessing memory systems within that level of cache without requiring explicit cache maintenance.
For accesses to non-cacheable Normal memory, the DMB instruction introduces a Barrier-ordered-before relationship over all accesses to individual peripherals or memory blocks of IMPLEMENTATION DEFINED size.
For Normal memory, the Arm architecture provides cache attributes that are independently defined for the two levels of cache concepts (the inner and the outer cache). The relationship between these conceptual levels of cache and the physical level caches implemented is IMPLEMENTATION DEFINED and can be distinguished from the boundaries between inner and outer shareable domains. However:
Inner refers to the innermost cache, which is closest to the PE and always includes the lowest level cache.
The cache controlled by the Inner cache attributes cannot be located outside the cache controlled by the Outer cache attributes.
In specific implementations, there may not be an outer cache. For instance, in a three-level cache architecture with L1, L2, and L3 caches, all three caches may be inner caches, with no outer cache. Alternatively, L1 may be an inner cache, while L2 and L3 are outer caches.
2. Device Memory
The Device memory type attributes define memory locations where accesses to those locations may lead to side effects, or the values returned from loads may vary based on the number of loads executed. Typically, Device memory attributes are used for memory-mapped peripherals and similar locations.
Device memory regions are generally used for some peripherals, such as USB UART modules, which are first non-cacheable, meaning that they do not go through the cache and access memory directly, with data only existing in memory and no backup elsewhere, ensuring the uniqueness and accuracy of the data. Secondly, the memory interaction of peripherals typically has high timing requirements, so read/write operations must be completed within a limited time. Additionally, apart from not going through the cache, accessing device memory may also lack other optimizations in memory access, such as speculative access. In summary, the memory attributes for peripherals need to meet the requirements of being timely, efficient, and accurate:
Speculative data accesses are not allowed for any memory location with any Device memory attribute. This means that every memory access to any Device memory type must be generated by the simple sequential execution of the program.
Writes to any Device memory type’s memory location must be completed within a limited time.
If the return value read from a Device memory type memory location changes without explicit memory writes affecting the observer, that change must also be globally observable to all observers in the system within a limited time. Such changes may occur in peripherals that hold status information.
Data accesses to Device memory locations are consistent for all observers in the system and are accordingly viewed as Outer Shareable.
Memory locations with any Device memory attribute cannot be allocated to caches.
For any Device memory type access, the DMB instruction introduces a Barrier-ordered-before relationship over all accesses to individual peripherals or specified sizes of memory blocks.
If a memory location cannot support unaligned memory accesses, then unaligned accesses to that memory location will generate alignment errors in the first stage of the conversion, defining that location as Device.
Hardware will not prevent speculative instruction fetches from memory locations with any Device memory attributes unless that memory location is also marked as execute-never for all exception levels.