1. What is the basic principle of I2C communication?A: I2C adopts a master-slave communication mechanism. The master device initiates and controls the communication, while the slave device responds to the master’s requests.
2. What are the key features of I2C communication?A: Supports multi-master and multi-slave architecture; requires only two communication lines; supports different transmission rates.
3. What are the two signal lines used by I2C?A: SDA (Serial Data Line) is used for data transmission; SCL (Serial Clock Line) is used for synchronizing clock signals.
4. What are the specific functions of SDA and SCL?A: SDA is a bidirectional data transmission channel for master and slave devices; SCL provides a synchronized clock signal to ensure data synchronization on the bus.
5. What are the operating modes of I2C?A: Standard mode (up to 100 kbit/s), fast mode (up to 400 kbit/s), high-speed mode (up to 3.4 Mbit/s).
6. Why is I2C called a “synchronous” protocol?A: Data transmission is synchronized by the SCL clock signal, with clock edges triggering data sampling.
7. What is the role of pull-up resistors?A: To ensure SDA/SCL remain high when no device is driving; to limit current and protect devices.
8. What limits the maximum length of the bus?A: Limited by bus capacitance, typically not exceeding a few meters in practical applications.
9. What is the definition of the start condition (START)?A: When SCL is high, a transition of SDA from high to low marks the beginning of communication.
10. What is the definition of the stop condition (STOP)?A: When SCL is high, a transition of SDA from low to high marks the end of communication.
11. How does the device addressing mechanism work?A: Each device has a unique 7-bit or 10-bit address, and the master device selects a specific slave device by address.
12. What elements are included in a data frame?A: Start condition + slave address + read/write bit + data byte (including acknowledgment bit) + stop condition.
13. What is the function of the acknowledgment bit (ACK)?A: The receiver (master or slave) pulls SDA low to confirm successful byte reception.
14. What is clock stretching?A: The slave device pulls SCL low to pause communication, allowing itself time to process.
15. How does a multi-master architecture avoid conflicts?A: By using a bus arbitration mechanism: when transmitting simultaneously, the master sending “1” while the other sends “0” will back off from arbitration.
16. How are devices on the bus identified?A: By scanning the 7-bit/10-bit address space, using I2C scanning tools to detect responding devices.
17. What does half-duplex characteristic mean?A: Supports bidirectional transmission, but only one-way data transmission can occur at the same time.
18. What could be the reasons for a slave device not responding?A: The slave device may be busy, there may be data reception errors, or hardware failures.
19. How is the communication rate determined?A: Determined by the clock frequency set by the master device, which must comply with the modes supported by the device (100k/400k/3.4M).
20. What are the core differences between I2C and SPI?A: I2C: two-wire, multi-master/slave, lower speed; SPI: four-wire, single master/multi-slave, higher speed.
21. What is the purpose of the repeated start condition?A: To change the data transmission direction or switch slave devices without releasing bus control.
22. What is the impact of bus capacitance?A: Excessive capacitance can slow down the rise time, limiting communication speed and transmission distance.
23. What measures can be taken to reduce noise?A: Optimize PCB layout, use shielded cables, and appropriately reduce communication speed.
24. What are the principles for selecting pull-up resistors?A: Calculated based on supply voltage, bus capacitance, and target speed, typical values are 1-10kΩ.
25. How to resolve level mismatch?A: Level shifters are needed between devices with different supply voltages.
26. What is the error detection mechanism?A: The protocol itself has no hardware error checking; it must be implemented through software verification.
27. What is the function of the general call address (0x00)?A: The master device broadcasts commands to all slave devices using this address.
28. What is the purpose of the bus clearing sequence?A: To resolve bus deadlock issues caused by SDA being accidentally pulled low.
29. What is the composition of the data packet format?A: Start bit + address bit + R/W bit + data byte (including ACK) + stop bit.
30. How is multi-master contention handled?A: Through an arbitration mechanism, the losing party automatically backs off and retries.
31. What are the conditions for releasing clock stretching?A: After the slave device completes processing, it releases SCL, allowing the pull-up resistor to restore high level.
32. Does point-to-point communication support?A: Supports the minimum system configuration of single master and single slave.
33. What is the relationship between SMBus and I2C?A: SMBus is a subset of I2C, designed for system management with stricter timing requirements.
34. What is the definition of the bus idle state?A: SDA and SCL are both held high.
35. What are the common troubleshooting steps?A: Check hardware connections, pull-up resistors, address configurations, and device statuses.
36. What could be the reasons for a slave device not responding?A: Power failure, address mismatch, device busy, or hardware damage.
37. What causes abnormal communication rates?A: Clock stretching, excessive bus capacitance, or overly large pull-up resistors can lead to actual rates being lower than set values.
38. What are the solutions for data inconsistency?A: Check for noise interference, rate and capacitance matching, and software processing logic.
39. What causes spikes on the falling edge of SCL?A: Usually caused by parasitic capacitance on the SCL line.
40. What are the diagnostic methods for lost ACK signals?A: Check if the SDA line is locked, the status of the slave device, and the integrity of data transmission.
41. What measures can be taken if the bus is pulled low?A: Investigate hardware failures (such as damaged devices) or software errors (abnormal bus occupation).
42. How to verify device addresses?A: Use I2C scanning tools to traverse the address space and confirm device responses.
43. Is hot-swapping supported?A: The protocol itself does not support it, which may cause bus anomalies, except for some specially designed devices.
44. What are the conditions for enabling high-speed mode (1 Mbps)?A: Devices must support the Fast-mode Plus specification and have optimized hardware design.
45. What should be noted when dynamically adjusting clock frequency?A: Adjustments must be made when the bus is idle to avoid timing issues for slave devices.
46. What are the consequences of removing a device during communication?A: It may cause the master device to hang, bus errors, or data corruption.
47. What are the risks of level incompatibility?A: Low-voltage devices may not recognize high-voltage signals, and high voltage may damage low-voltage devices.
48. What are the enhanced anti-interference solutions?A: Shorten trace distances, use shielding measures, and in extreme noise environments, consider using RS-485 or CAN bus.
49. What are the solutions for failures caused by an increase in devices?A: Reduce the value of pull-up resistors to compensate for increased bus capacitance, or use bus repeaters.
50. What methods can be used to extend the maximum transmission distance?A: Enhance signals using bus buffers/extenders, or switch to communication protocols more suitable for long distances.
51. What are the methods for testing device functionality?A: Use I2C debugging tools to send test commands and verify device responses against the data sheet.
52. What is the chain effect of a faulty device?A: A single device failure (such as continuously pulling the bus low) can cause the entire system to fail.
53. What are the key points for selecting level shifters?A: Must support bidirectional transmission, and the conversion rate must meet I2C communication requirements.
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