Everyone knows that making a PCB involves turning a well-designed schematic into a tangible PCB circuit board. Please do not underestimate this process; many things that work in theory can be difficult to achieve in practice, or some things that others can realize, others cannot. Thus, while making a PCB is not difficult, making a good PCB is not an easy task.
Two major challenges in the microelectronics field are handling high-frequency signals and weak signals. In this regard, the level of PCB fabrication is particularly important. With the same design principles and components, PCBs made by different individuals can yield different results. So how can we make a good PCB?
Based on our previous experiences, I would like to discuss the following aspects:
1Clarify Design Objectives
Upon receiving a design task, the first step is to clarify its design objectives. Is it a standard PCB, a high-frequency PCB, a small signal processing PCB, or one that handles both high frequency and small signal processing? If it is a standard PCB, it is sufficient to ensure that the layout and routing are reasonable and tidy, and that the mechanical dimensions are accurate. If there are medium load lines and long lines, certain methods must be adopted to alleviate the load, and long lines must be driven more strongly, with a focus on preventing long line reflections.
When there are signal lines exceeding 40MHz on the board, special considerations must be given to these signal lines, such as crosstalk issues. If the frequency is even higher, there are stricter limits on the routing length. According to distributed parameter network theory, the interaction between high-speed circuits and their connections is a decisive factor that cannot be ignored in system design. As gate transmission speeds increase, the opposition on signal lines will correspondingly increase, and crosstalk between adjacent signal lines will increase proportionally. Generally, high-speed circuits also have significant power consumption and heat dissipation, so adequate attention must be paid when making high-speed PCBs.
When there are millivolt or even microvolt level weak signals on the board, special care must be taken with these signal lines. Small signals are very weak and are easily disturbed by other strong signals, making shielding measures often necessary; otherwise, the signal-to-noise ratio will be significantly reduced, causing useful signals to be drowned out by noise and unable to be effectively extracted.Testing of the board must also be considered during the design phase, as the physical location of test points and the isolation of test points cannot be overlooked. This is because some small signals and high-frequency signals cannot be measured directly by attaching probes.Additionally, other related factors must be considered, such as the number of layers in the board, the packaging shape of the components used, and the mechanical strength of the board. Before making a PCB, one must have a clear understanding of the design objectives.
2Understand Component Functionality Requirements for Layout and Routing
We know that some special components have specific requirements for layout and routing. For example, the analog signal amplifiers used in LOTI and APH require stable power supplies with low ripple. The analog small signal parts should be placed as far away from power devices as possible. On the OTI board, the small signal amplification section is specifically equipped with a shielding cover to block stray electromagnetic interference.
The GLINK chip used on the NTOI board employs ECL technology, which generates significant heat. Therefore, special consideration must be given to heat dissipation during layout. If natural cooling is used, the GLINK chip should be placed in an area with good air circulation, and the heat generated should not adversely affect other chips. If the board is equipped with speakers or other high-power devices, it is also essential to pay attention to the potential for serious power supply contamination.
3Considerations for Component Layout
The first factor to consider in component layout is electrical performance. Components that are closely related in terms of connections should be placed together as much as possible, especially for high-speed lines, where the layout should be kept as short as possible. Power signal and small signal devices should be separated. While meeting circuit performance requirements, the layout should also consider neatness, aesthetics, ease of testing, and the mechanical dimensions and positions of sockets on the board.
In high-speed systems, grounding and transmission delay times on interconnect lines are also primary considerations in system design. The transmission time on signal lines significantly impacts overall system speed, especially for high-speed ECL circuits. Although the integrated circuit blocks themselves have high speeds, using standard interconnect lines on the substrate (with about 2ns delay for every 30cm of line length) can introduce delays that significantly lower system speed.
For synchronous working components like shift registers and synchronous counters, it is best to place them on the same plug-in board. This is because the transmission delay times for clock signals to different plug-in boards are not equal, which can lead to errors in the shift register operation. If they cannot be placed on the same board, the lengths of clock lines from a common clock source to each plug-in board must be equal at critical synchronization points.
4Considerations for Routing
With the completion of OTNI and star fiber optic network designs, there will be more boards with high-speed signal lines exceeding 100MHz that need to be designed. Here, I will introduce some basic concepts of high-speed lines.
Transmission Lines
Any “long” signal path on a printed circuit board can be regarded as a transmission line. If the transmission delay time of the line is much shorter than the signal rise time, then the reflections generated during the signal rise will be drowned out. Overshoot, undershoot, and ringing will not be present. For most MOS circuits today, since the rise time is much greater than the line transmission delay time, the traces can be several meters long without signal distortion. However, for faster logic circuits, especially ultra-high-speed ECL integrated circuits, due to the increased edge speed, if no other measures are taken, the length of the traces must be significantly reduced to maintain signal integrity.
There are two methods to allow high-speed circuits to operate on relatively long lines without severe waveform distortion. The TTL method uses Schottky diodes for fast falling edges to clamp overshoot to a level lower than ground potential by one diode drop, which reduces the amplitude of undershoot. Slower rising edges allow for overshoot, but it is attenuated by the relatively high output impedance (50-80Ω) of the circuit in the “H” state. Moreover, since the “H” state is relatively resistant to interference, the undershoot issue is not very prominent. For HCT series devices, using a combination of Schottky diode clamping and series resistance termination methods will yield even more noticeable improvements.
When there is fan-out along the signal line at higher bit rates and faster edge rates, the aforementioned TTL shaping methods may prove insufficient. This is because reflections present in the lines will tend to combine at high bit rates, leading to severe signal distortion and reduced interference immunity. Therefore, to address reflection issues, another method is commonly used in ECL systems: line impedance matching. This method can control reflections and ensure signal integrity.
Strictly speaking, for conventional TTL and CMOS devices with slower edge speeds, transmission lines are not particularly necessary. For high-speed ECL devices with faster edge speeds, transmission lines are not always required. However, when transmission lines are used, they have the advantage of being able to predict interconnection delays and control reflections and ringing through impedance matching.
1. The basic factors determining whether to use transmission lines are as follows:
(1) The edge rate of system signals;
(2) Interconnection distance;
(3) Capacitive load (amount of fan-out);
(4) Resistive load (termination method of the line);
(5) Allowed percentage of undershoot and overshoot (degree of attenuation of AC immunity).
2. Types of Transmission Lines
(1) Coaxial cables and twisted pairs: They are often used for connections between systems. The characteristic impedance of coaxial cables is usually 50Ω and 75Ω, while twisted pair is typically 110Ω.
(2) Microstrip lines on printed boards
Microstrip is a strip conductor (signal line) isolated from the ground plane by a dielectric. If the thickness, width, and distance from the ground plane are controllable, then its characteristic impedance can also be controlled. The characteristic impedance Z0 of microstrip lines is:
(3) Strip lines in printed boards
Strip lines are copper strip lines placed in a dielectric between two layers of conductive planes. If the thickness and width of the lines, the dielectric constant of the medium, and the distance between the two conductive planes are controllable, then the characteristic impedance of the strip lines can also be controlled. The characteristic impedance of strip lines is:
3. Terminating Transmission Lines
When a resistor equal to the characteristic impedance of the line is connected at the receiving end of a line, it is referred to as a parallel termination. This is primarily to achieve the best electrical performance, including driving distributed loads.
Sometimes, to save power consumption, a capacitor of 104 is connected in series with the terminating resistor to form an AC termination circuit, which can effectively reduce DC losses.
A resistor is connected in series between the driver and the transmission line, and the line’s end is no longer connected to a terminating resistor; this termination method is referred to as series termination. Overshoot and ringing on longer lines can be controlled using series damping or series termination techniques. Series damping is achieved using a small resistor (generally 10-75Ω) in series with the driver output. This damping method is suitable for use with lines where characteristic impedance is controlled (e.g., substrate routing, circuits without ground planes, and most winding lines).
In series termination, the value of the series resistor plus the output impedance of the driver equals the characteristic impedance of the transmission line. However, series termination has the drawback of only being usable with lumped loads at the terminal and longer transmission delays. This can be overcome by using excess series termination transmission lines.4. Non-terminated Transmission Lines
If the delay time of the line is much shorter than the signal rise time, transmission lines can be used without series or parallel termination. If the round-trip delay time of a non-terminated line (the time it takes for a signal to travel to the end of the line and back) is shorter than the rise time of the pulse signal, then the undershoot caused by non-termination is approximately 15% of the logic swing. The maximum open line length is approximately:
Lmax<tr/2tpd
Where: tr is the rise time
tpd is the transmission delay time per unit length
5. Comparison of Various Termination Methods
Both parallel termination and series termination have their advantages. Which one to use, or whether to use both, depends on the designer’s preference and the system requirements. The main advantage of parallel termination is the fast system speed and lossless signal transmission over the line. Loads on long lines do not affect the transmission delay time of the driver driving the long line, nor do they affect its signal edge speed, but they will increase the transmission delay time along the long line. In driving large fan-out, loads can be distributed along branch short lines, rather than having to be concentrated at the terminal of the line as in series termination.
Series termination allows the circuit to drive several parallel load lines. The delay time increase caused by capacitive loads in series termination is about twice that of the corresponding parallel termination, while short lines may slow the edge speed and increase the driver delay time due to capacitive loads. However, the crosstalk in series termination is less than that in parallel termination, mainly because the signal amplitude transmitted along the series termination line is only half of the logic swing, and thus the switching current is also only half of that in parallel termination, resulting in smaller signal energy and less crosstalk.
When making PCBs, whether to choose double-sided boards or multilayer boards depends on the maximum operating frequency, the complexity of the circuit system, and the requirements for assembly density. When the clock frequency exceeds 200MHz, it is best to choose multilayer boards. If the operating frequency exceeds 350MHz, it is best to select printed circuit boards with polytetrafluoroethylene as the dielectric layer, as they have lower high-frequency loss, smaller parasitic capacitance, faster transmission speeds, and lower power consumption due to a larger Z0.
The routing of printed circuit boards has the following principles:
(1) All parallel signal lines should maintain a large gap to reduce crosstalk. If there are two closely spaced signal lines, it is best to route a ground line between the two, which can serve as shielding.
(2) When designing signal transmission lines, avoid sharp turns to prevent sudden changes in transmission line characteristic impedance, which can cause reflections. Design should aim for uniform arcs of a certain size.
(3) The width of printed lines can be calculated based on the characteristic impedance formulas for microstrip and strip lines mentioned above. The characteristic impedance of microstrip lines on printed circuit boards is generally between 50-120Ω. To achieve a larger characteristic impedance, the line width must be very narrow, but very thin lines are not easy to manufacture.
Considering various factors, a characteristic impedance value of around 68Ω is generally suitable, as it provides the best balance between delay time and power consumption. A 50Ω transmission line will consume more power; while a larger impedance will reduce power consumption, it will also increase transmission delay time.
Negative line capacitance can cause an increase in transmission delay time and a decrease in characteristic impedance. However, segments with very low characteristic impedance have relatively large intrinsic capacitance per unit length, so their transmission delay time and characteristic impedance are less affected by load capacitance. An important feature of transmission lines with appropriate termination is that branch short lines should have little impact on line delay time. When Z0 is 50Ω, the length of branch short lines must be limited to within 2.5cm to avoid significant ringing.
(4) For double-sided boards (or four-layer lines in six-layer boards), the lines on both sides of the circuit board should be perpendicular to each other to prevent mutual induction from causing crosstalk.
(5) If there are large current devices on the printed board, such as relays, indicator lights, or speakers, their ground lines should be routed separately to reduce noise on the ground lines. The ground lines of these large current devices should be connected to an independent ground bus on the plug-in board and backplane, and these independent ground lines should also be connected to the overall system ground point.
(6) If there are small signal amplifiers on the board, the weak signal lines before amplification should be kept away from strong signal lines, and the routing should be as short as possible. If possible, ground lines should also be used for shielding.
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