High-Speed Sampling and Conversion of ADC (Part 2)

When performing ADC acquisition on STM32, the difference in time efficiency between using software (interrupt or polling) to transfer data and using DMA to transfer data is very significant. This difference is mainly reflected in CPU time consumption and system responsiveness, rather than the time taken for a single sampling conversion itself. For example, consider acquiring 3 ADC channels, with each channel requiring 16 samples for filtering.

1.Core Difference: CPU Involvement

1.1 Software Transfer (Interrupt/Polling)

Interrupt Method: An interrupt is generated every time an ADC conversion is completed. The CPU must pause the current task, save the context, jump to the Interrupt Service Routine (ISR), read data from the ADC data register (such asADCx->DR), store it in the target array, and then restore the context and return. This process involves multiple instructions and bus accesses.

Polling Method: The CPU needs to continuously check (in a while loop) the ADC status register(such asADCx->SR for theEOC flag). When the conversion is detected as complete, the CPU reads the data register and stores it. This also requires the CPU to continuously participate in checking the status and transferring data.

1.2 DMA Transfer

ADC conversion complete signals directly trigger the DMA controller.The DMA controller automatically transfers data from theADCx->DR register to a specified memory address (such as an array) without any CPU intervention. The CPU can continue executing the main program code or other tasks, and only when the entire DMA transfer is complete (or half transfer) may an interrupt notify the CPU for subsequent processing (such as calculations or transmissions).

2.Estimation of Time Differences

2.1 Time Taken for Single Data Transfer (Software vs DMA)

2.1.1 Software Transfer (Interrupt Method)

This is the most time-consuming. The response and processing time for a single interrupt (including context saving/restoring, status checking, data reading, and data storing) typically requires dozens to hundreds of CPU clock cycles. The specifics depend on:

Type of CPU core (M0, M3, etc. have different performances)
CPU clock frequency (higher frequency, faster speed)
Compiler optimization level (higher optimization, faster speed)
Interrupt nesting situation (less nesting, faster speed)
Location of stored data (SRAM is faster, but access also requires cycles).

A conservative estimate: on a typical72MHz@Cortex-M3/M4, a simple ADC interrupt service routine (only reading DR and storing to memory) may consume 20 – 100 cycles. The time range is approximately 0.28μs (20/72M) to 1.39μs (100/72M).

2.1.2 Software Transfer (Polling Method)

This is slightly better than the interrupt method, avoiding interrupt overhead, but the CPU must continuously poll the status bit. The polling loop itself (checking status, conditional jumps) also requires several cycles. When the conversion is complete, reading the data storage also requires cycles. Effective data transfer may be slightly faster than the interrupt method (avoiding context switching), but the CPU is fully occupied doing useless work during the wait, leading to very low efficiency. A single effective operation may take 10 – 50 cycles (0.14μs – 0.69μs @72MHz), but the CPU occupancy during the wait is 100%.

2.1.3 DMA Automatic Transfer

The overhead for a single transfer is 0 cycles for the CPU. The DMA controller uses the system bus to complete data transfer from peripherals to memory in the background. This transfer operation itself also requires bus time (usually 1 to several cycles, depending on bus architecture and arbitration), but this does not occupy CPU time at all. The CPU can execute other code in parallel. DMA configuration is completed once during initialization.

3. Determinism of Software Tasks

3.1 Task Cycle is Determined but Response is Slowest

If it is a single, non-scanning working mode of the ADC, then the software must control the timing of starting the ADC, for example, starting the ADC acquisition of this channel 16 times every1ms, meaning 16 cycles of ADC start within 1ms, followed by software filtering and calculations on the 16 data points (if the computation time is not too long, it can be placed in the interrupt; if longer, it needs to be placed in a while loop), and then providing the calculation results to other peripherals, such as to the DA peripheral. The advantage of this periodic ADC start is that it can determine what each peripheral is doing at each moment, providing good determinism, but due to the scheduling cycle, it also means that the highest response speed to external analog changes is not achieved.

3.2 Task Cycle is Uncertain but Response is Fastest

If it is a continuous, scanning working mode of the ADC, combined with DMA transferring the ADC data register values to SRAM, the CPU can directly use the transferred data while DMA is transferring, saving the transfer operation. In this case, the response speed depends on the CPU’s computation and processing of the data (the fastest response is when placed in awhile<code> loop). Assuming DMA transfer time is very low, and CPU computation time is relatively high. To achieve the fastest response, the ADC is set to continuous mode, which also means that there is no manually controlled task cycle in the software; instead, it is entirely determined by the hardware's performance (sampling, conversion, transfer time), which defines the execution cycle of a task, thus reaching the upper limit of response speed. Therefore, this is a downside.

3.3 Task Cycle is Determined but Response is Relatively Fast

If extreme response speed is not required, to balance response speed and task cycle determinism, a timer can generally be used to trigger the start ofADC sampling. At this time, theADC<code> can be set to single, scanning mode, thus<code>ADC<code> becomes periodic sampling, and combined with<code>DMA<code> transferring data to<code>SRAM<code>,<code> the CPU<code> does not need to participate, and is completely handled automatically by these peripherals, saving<code>CPU<code> resources. The CPU only needs to focus on<code>ADC<code> data computation and processing.

4. About DMA Double Buffer Configuration

4.1 Configure ADC for Scanning Continuous Mode

Configure the ADC for scanning continuous mode, using DMA circular transfer, configured for 3 channels, with each channel sampling 16 times (a total of 48 conversions). The DMA is set to double buffer mode, transferring 48 samples each time (48 samples per buffer). This ensures that each time DMA completes a round, it fulfills a round of ADC acquisition as required: each of the 3 channels samples 16 times..

4.2 DMA Half Transfer Complete Interrupt

When the DMA half transfer complete interrupt occurs (i.e., 24 samples, corresponding to 8 samples for each channel), process the first 24 samples, but since each channel requires 16 samples, it is necessary to wait for the full transfer to complete. Therefore, it should be modified to: The DMA buffer length can be set to 96 (32 samples for each channel), and then the half buffer will be 48 samples (16 samples for each channel). Thus, when the half transfer interrupt occurs, we process the first 48 samples (16 samples for each channel), while DMA continues to fill the next 48 samples..4.2 Dual ADC Working Independently If one of the 3 channels, say channel 1, requires fast acquisition speed and response speed, while the other two can be slower, then using this 3-channel scanning method is not the fastest, because the DMA must transfer 48 times before the data from ADC channel 1 can be used. The best approach would be to use 2 ADC modules, one for the high-speed sampling and quick response ADC channel 1, which can be configured as an injected group with corresponding DMA transfer; the other for the normal sampling ADC channels 2 and 3, configured as a regular group. If DMA resources are sufficient, it can be configured for DMA; otherwise, software reading can be used.

5. Summary Points

5.1 Time Differences

The time saved by DMA compared to software transfer (especially interrupt method) is mainly reflected in the liberation of CPU time. For 16 transfers:

Software Interrupt: CPU spends11μs on interrupt handling and data transfer.
DMA: CPU spends0μs on data transfer (only one optional completion interrupt, with very little overhead).

Thus, DMA saves the CPU approximately 11μs (in this specific estimated scenario) to perform other tasks. This difference will increase linearly with the number of samples.

5.2 System Impact

5.2.1 Software Transfer

Software transfer (especially high-frequency interrupts) significantly increases CPU load, which may lead to:

Slower execution of the main loop, i.e., longer loop cycles, as CPU time is consumed by data transfer, resulting in sluggish system response.
Other lower-priority tasks or interrupts being delayed or lost, as CPU time is consumed by data transfer.
At high sampling rates or multi-channel sampling, the CPU may become overloaded and unable to read data in time, leading to ADC data register overflow and data loss.

5.2.2 Advantages of DMA

Extremely low CPU overhead liberates CPU processing time and capability.
Determinism of transfer time

DMA transfer time is more predictable, unaffected by interrupt delays and task scheduling.

Suitable for high-speed/continuous sampling

Easily handles data streams from high sampling rates, multi-channel scanning, or continuous modes..

Reduced CPU power consumption CPU can spend more time in low-power modes.

5.3 Conclusion

For ADC acquisition on STM32, using DMA to transfer data compared to software transfer (especially interrupt method) has an overwhelming advantage in time efficiency. Software interrupt transfer of 16 ADC values may require the CPU to spend tens of microseconds (depending on CPU speed and code efficiency), and it incurs significant interrupt overhead and system latency. In contrast, DMA reduces this overhead to almost zero (only one optional transfer complete interrupt), allowing the CPU to focus on other tasks, greatly improving the overall efficiency and responsiveness of the system. In applications requiring continuous, high-speed, or multi-channel ADC acquisition, using DMA is strongly recommended.